intr_control.cc revision 2665:a124942bacb8 
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Nathan Binkert
29 *          Ron Dreslinski
30 */
31
32#include <string>
33#include <vector>
34
35#include "cpu/base.hh"
36#include "cpu/exec_context.hh"
37#include "cpu/intr_control.hh"
38#include "sim/builder.hh"
39#include "sim/sim_object.hh"
40
41using namespace std;
42
43IntrControl::IntrControl(const string &name, BaseCPU *c)
44    : SimObject(name), cpu(c)
45{}
46
47/* @todo
48 *Fix the cpu sim object parameter to be a system pointer
49 *instead, to avoid some extra dereferencing
50 */
51void
52IntrControl::post(int int_num, int index)
53{
54    std::vector<ExecContext *> &xcvec = cpu->system->execContexts;
55    BaseCPU *temp = xcvec[0]->getCpuPtr();
56    temp->post_interrupt(int_num, index);
57}
58
59void
60IntrControl::post(int cpu_id, int int_num, int index)
61{
62    std::vector<ExecContext *> &xcvec = cpu->system->execContexts;
63    BaseCPU *temp = xcvec[cpu_id]->getCpuPtr();
64    temp->post_interrupt(int_num, index);
65}
66
67void
68IntrControl::clear(int int_num, int index)
69{
70    std::vector<ExecContext *> &xcvec = cpu->system->execContexts;
71    BaseCPU *temp = xcvec[0]->getCpuPtr();
72    temp->clear_interrupt(int_num, index);
73}
74
75void
76IntrControl::clear(int cpu_id, int int_num, int index)
77{
78    std::vector<ExecContext *> &xcvec = cpu->system->execContexts;
79    BaseCPU *temp = xcvec[cpu_id]->getCpuPtr();
80    temp->clear_interrupt(int_num, index);
81}
82
83BEGIN_DECLARE_SIM_OBJECT_PARAMS(IntrControl)
84
85    SimObjectParam<BaseCPU *> cpu;
86
87END_DECLARE_SIM_OBJECT_PARAMS(IntrControl)
88
89BEGIN_INIT_SIM_OBJECT_PARAMS(IntrControl)
90
91    INIT_PARAM(cpu, "the cpu")
92
93END_INIT_SIM_OBJECT_PARAMS(IntrControl)
94
95CREATE_SIM_OBJECT(IntrControl)
96{
97    return new IntrControl(getInstanceName(), cpu);
98}
99
100REGISTER_SIM_OBJECT("IntrControl", IntrControl)
101