intr_control.cc revision 2632:1bb2f91485ea 
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <string>
30#include <vector>
31
32#include "cpu/base.hh"
33#include "cpu/exec_context.hh"
34#include "cpu/intr_control.hh"
35#include "sim/builder.hh"
36#include "sim/sim_object.hh"
37
38using namespace std;
39
40IntrControl::IntrControl(const string &name, BaseCPU *c)
41    : SimObject(name), cpu(c)
42{}
43
44/* @todo
45 *Fix the cpu sim object parameter to be a system pointer
46 *instead, to avoid some extra dereferencing
47 */
48void
49IntrControl::post(int int_num, int index)
50{
51    std::vector<ExecContext *> &xcvec = cpu->system->execContexts;
52    BaseCPU *temp = xcvec[0]->getCpuPtr();
53    temp->post_interrupt(int_num, index);
54}
55
56void
57IntrControl::post(int cpu_id, int int_num, int index)
58{
59    std::vector<ExecContext *> &xcvec = cpu->system->execContexts;
60    BaseCPU *temp = xcvec[cpu_id]->getCpuPtr();
61    temp->post_interrupt(int_num, index);
62}
63
64void
65IntrControl::clear(int int_num, int index)
66{
67    std::vector<ExecContext *> &xcvec = cpu->system->execContexts;
68    BaseCPU *temp = xcvec[0]->getCpuPtr();
69    temp->clear_interrupt(int_num, index);
70}
71
72void
73IntrControl::clear(int cpu_id, int int_num, int index)
74{
75    std::vector<ExecContext *> &xcvec = cpu->system->execContexts;
76    BaseCPU *temp = xcvec[cpu_id]->getCpuPtr();
77    temp->clear_interrupt(int_num, index);
78}
79
80BEGIN_DECLARE_SIM_OBJECT_PARAMS(IntrControl)
81
82    SimObjectParam<BaseCPU *> cpu;
83
84END_DECLARE_SIM_OBJECT_PARAMS(IntrControl)
85
86BEGIN_INIT_SIM_OBJECT_PARAMS(IntrControl)
87
88    INIT_PARAM(cpu, "the cpu")
89
90END_INIT_SIM_OBJECT_PARAMS(IntrControl)
91
92CREATE_SIM_OBJECT(IntrControl)
93{
94    return new IntrControl(getInstanceName(), cpu);
95}
96
97REGISTER_SIM_OBJECT("IntrControl", IntrControl)
98