intr_control.cc revision 4762
12SN/A/* 21762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Nathan Binkert 292665Ssaidi@eecs.umich.edu * Ron Dreslinski 302SN/A */ 312SN/A 322SN/A#include <string> 332SN/A#include <vector> 342SN/A 351717SN/A#include "cpu/base.hh" 362680Sktlim@umich.edu#include "cpu/thread_context.hh" 3756SN/A#include "cpu/intr_control.hh" 384762Snate@binkert.org#include "params/IntrControl.hh" 3956SN/A#include "sim/sim_object.hh" 402SN/A 412SN/Ausing namespace std; 422SN/A 434103Ssaidi@eecs.umich.eduIntrControl::IntrControl(const string &name, System *s) 444103Ssaidi@eecs.umich.edu : SimObject(name), sys(s) 452SN/A{} 462SN/A 47295SN/Avoid 48295SN/AIntrControl::post(int int_num, int index) 49295SN/A{ 504103Ssaidi@eecs.umich.edu std::vector<ThreadContext *> &tcvec = sys->threadContexts; 512680Sktlim@umich.edu BaseCPU *temp = tcvec[0]->getCpuPtr(); 52295SN/A temp->post_interrupt(int_num, index); 53295SN/A} 54295SN/A 55295SN/Avoid 56295SN/AIntrControl::post(int cpu_id, int int_num, int index) 57295SN/A{ 584103Ssaidi@eecs.umich.edu std::vector<ThreadContext *> &tcvec = sys->threadContexts; 592680Sktlim@umich.edu BaseCPU *temp = tcvec[cpu_id]->getCpuPtr(); 60295SN/A temp->post_interrupt(int_num, index); 61295SN/A} 62295SN/A 63295SN/Avoid 64295SN/AIntrControl::clear(int int_num, int index) 65295SN/A{ 664103Ssaidi@eecs.umich.edu std::vector<ThreadContext *> &tcvec = sys->threadContexts; 672680Sktlim@umich.edu BaseCPU *temp = tcvec[0]->getCpuPtr(); 68295SN/A temp->clear_interrupt(int_num, index); 69295SN/A} 70295SN/A 71295SN/Avoid 72295SN/AIntrControl::clear(int cpu_id, int int_num, int index) 73295SN/A{ 744103Ssaidi@eecs.umich.edu std::vector<ThreadContext *> &tcvec = sys->threadContexts; 752680Sktlim@umich.edu BaseCPU *temp = tcvec[cpu_id]->getCpuPtr(); 76295SN/A temp->clear_interrupt(int_num, index); 77295SN/A} 78295SN/A 794762Snate@binkert.orgIntrControl * 804762Snate@binkert.orgIntrControlParams::create() 812SN/A{ 824762Snate@binkert.org return new IntrControl(name, sys); 832SN/A} 84