intr_control.cc revision 2680
12SN/A/* 21762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Nathan Binkert 292665Ssaidi@eecs.umich.edu * Ron Dreslinski 302SN/A */ 312SN/A 322SN/A#include <string> 332SN/A#include <vector> 342SN/A 351717SN/A#include "cpu/base.hh" 362680Sktlim@umich.edu#include "cpu/thread_context.hh" 3756SN/A#include "cpu/intr_control.hh" 38146SN/A#include "sim/builder.hh" 3956SN/A#include "sim/sim_object.hh" 402SN/A 412SN/Ausing namespace std; 422SN/A 432SN/AIntrControl::IntrControl(const string &name, BaseCPU *c) 442SN/A : SimObject(name), cpu(c) 452SN/A{} 462SN/A 47295SN/A/* @todo 48295SN/A *Fix the cpu sim object parameter to be a system pointer 49295SN/A *instead, to avoid some extra dereferencing 50295SN/A */ 51295SN/Avoid 52295SN/AIntrControl::post(int int_num, int index) 53295SN/A{ 542680Sktlim@umich.edu std::vector<ThreadContext *> &tcvec = cpu->system->threadContexts; 552680Sktlim@umich.edu BaseCPU *temp = tcvec[0]->getCpuPtr(); 56295SN/A temp->post_interrupt(int_num, index); 57295SN/A} 58295SN/A 59295SN/Avoid 60295SN/AIntrControl::post(int cpu_id, int int_num, int index) 61295SN/A{ 622680Sktlim@umich.edu std::vector<ThreadContext *> &tcvec = cpu->system->threadContexts; 632680Sktlim@umich.edu BaseCPU *temp = tcvec[cpu_id]->getCpuPtr(); 64295SN/A temp->post_interrupt(int_num, index); 65295SN/A} 66295SN/A 67295SN/Avoid 68295SN/AIntrControl::clear(int int_num, int index) 69295SN/A{ 702680Sktlim@umich.edu std::vector<ThreadContext *> &tcvec = cpu->system->threadContexts; 712680Sktlim@umich.edu BaseCPU *temp = tcvec[0]->getCpuPtr(); 72295SN/A temp->clear_interrupt(int_num, index); 73295SN/A} 74295SN/A 75295SN/Avoid 76295SN/AIntrControl::clear(int cpu_id, int int_num, int index) 77295SN/A{ 782680Sktlim@umich.edu std::vector<ThreadContext *> &tcvec = cpu->system->threadContexts; 792680Sktlim@umich.edu BaseCPU *temp = tcvec[cpu_id]->getCpuPtr(); 80295SN/A temp->clear_interrupt(int_num, index); 81295SN/A} 82295SN/A 832SN/ABEGIN_DECLARE_SIM_OBJECT_PARAMS(IntrControl) 842SN/A 852SN/A SimObjectParam<BaseCPU *> cpu; 862SN/A 872SN/AEND_DECLARE_SIM_OBJECT_PARAMS(IntrControl) 882SN/A 892SN/ABEGIN_INIT_SIM_OBJECT_PARAMS(IntrControl) 902SN/A 91295SN/A INIT_PARAM(cpu, "the cpu") 922SN/A 932SN/AEND_INIT_SIM_OBJECT_PARAMS(IntrControl) 942SN/A 952SN/ACREATE_SIM_OBJECT(IntrControl) 962SN/A{ 972SN/A return new IntrControl(getInstanceName(), cpu); 982SN/A} 992SN/A 1002SN/AREGISTER_SIM_OBJECT("IntrControl", IntrControl) 101