intr_control.cc revision 1762
11060SN/A/* 27944SGiacomo.Gabrielli@arm.com * Copyright (c) 2002-2005 The Regents of The University of Michigan 37944SGiacomo.Gabrielli@arm.com * All rights reserved. 47944SGiacomo.Gabrielli@arm.com * 57944SGiacomo.Gabrielli@arm.com * Redistribution and use in source and binary forms, with or without 67944SGiacomo.Gabrielli@arm.com * modification, are permitted provided that the following conditions are 77944SGiacomo.Gabrielli@arm.com * met: redistributions of source code must retain the above copyright 87944SGiacomo.Gabrielli@arm.com * notice, this list of conditions and the following disclaimer; 97944SGiacomo.Gabrielli@arm.com * redistributions in binary form must reproduce the above copyright 107944SGiacomo.Gabrielli@arm.com * notice, this list of conditions and the following disclaimer in the 117944SGiacomo.Gabrielli@arm.com * documentation and/or other materials provided with the distribution; 127944SGiacomo.Gabrielli@arm.com * neither the name of the copyright holders nor the names of its 137944SGiacomo.Gabrielli@arm.com * contributors may be used to endorse or promote products derived from 142702SN/A * this software without specific prior written permission. 151060SN/A * 161060SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171060SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181060SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191060SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201060SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211060SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221060SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231060SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241060SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251060SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261060SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 271060SN/A */ 281060SN/A 291060SN/A#include <string> 301060SN/A#include <vector> 311060SN/A 321060SN/A#include "cpu/base.hh" 331060SN/A#include "cpu/intr_control.hh" 341060SN/A#include "sim/builder.hh" 351060SN/A#include "sim/sim_object.hh" 361060SN/A 371060SN/Ausing namespace std; 381060SN/A 392665SN/AIntrControl::IntrControl(const string &name, BaseCPU *c) 402665SN/A : SimObject(name), cpu(c) 411060SN/A{} 421060SN/A 439944Smatt.horsnell@ARM.com/* @todo 449944Smatt.horsnell@ARM.com *Fix the cpu sim object parameter to be a system pointer 459944Smatt.horsnell@ARM.com *instead, to avoid some extra dereferencing 461060SN/A */ 472292SN/Avoid 488229Snate@binkert.orgIntrControl::post(int int_num, int index) 491060SN/A{ 501060SN/A std::vector<ExecContext *> &xcvec = cpu->system->execContexts; 511060SN/A BaseCPU *temp = xcvec[0]->cpu; 521061SN/A temp->post_interrupt(int_num, index); 536658Snate@binkert.org} 546658Snate@binkert.org 551060SN/Avoid 568232Snate@binkert.orgIntrControl::post(int cpu_id, int int_num, int index) 578232Snate@binkert.org{ 582669SN/A std::vector<ExecContext *> &xcvec = cpu->system->execContexts; 596658Snate@binkert.org BaseCPU *temp = xcvec[cpu_id]->cpu; 601060SN/A temp->post_interrupt(int_num, index); 611061SN/A} 6210417Sandreas.hansson@arm.com 6310417Sandreas.hansson@arm.comvoid 647720Sgblack@eecs.umich.eduIntrControl::clear(int int_num, int index) 653794Sgblack@eecs.umich.edu{ 6613453Srekai.gonzalezalberquilla@arm.com std::vector<ExecContext *> &xcvec = cpu->system->execContexts; 6713453Srekai.gonzalezalberquilla@arm.com BaseCPU *temp = xcvec[0]->cpu; 6813453Srekai.gonzalezalberquilla@arm.com temp->clear_interrupt(int_num, index); 6913453Srekai.gonzalezalberquilla@arm.com} 7013453Srekai.gonzalezalberquilla@arm.com 7113453Srekai.gonzalezalberquilla@arm.comvoid 7213453Srekai.gonzalezalberquilla@arm.comIntrControl::clear(int cpu_id, int int_num, int index) 7313453Srekai.gonzalezalberquilla@arm.com{ 7413453Srekai.gonzalezalberquilla@arm.com std::vector<ExecContext *> &xcvec = cpu->system->execContexts; 751060SN/A BaseCPU *temp = xcvec[cpu_id]->cpu; 761464SN/A temp->clear_interrupt(int_num, index); 771061SN/A} 787720Sgblack@eecs.umich.edu 797720Sgblack@eecs.umich.eduBEGIN_DECLARE_SIM_OBJECT_PARAMS(IntrControl) 804636Sgblack@eecs.umich.edu 814636Sgblack@eecs.umich.edu SimObjectParam<BaseCPU *> cpu; 824636Sgblack@eecs.umich.edu 834636Sgblack@eecs.umich.eduEND_DECLARE_SIM_OBJECT_PARAMS(IntrControl) 844636Sgblack@eecs.umich.edu 8510417Sandreas.hansson@arm.comBEGIN_INIT_SIM_OBJECT_PARAMS(IntrControl) 8610417Sandreas.hansson@arm.com 879046SAli.Saidi@ARM.com INIT_PARAM(cpu, "the cpu") 881464SN/A 892292SN/AEND_INIT_SIM_OBJECT_PARAMS(IntrControl) 901464SN/A 911464SN/ACREATE_SIM_OBJECT(IntrControl) 921464SN/A{ 931464SN/A return new IntrControl(getInstanceName(), cpu); 941464SN/A} 951464SN/A 961464SN/AREGISTER_SIM_OBJECT("IntrControl", IntrControl) 972678SN/A