intr_control.cc revision 1717
112855Sgabeblack@google.com/* 212855Sgabeblack@google.com * Copyright (c) 2002-2003 The Regents of The University of Michigan 312855Sgabeblack@google.com * All rights reserved. 412855Sgabeblack@google.com * 512855Sgabeblack@google.com * Redistribution and use in source and binary forms, with or without 612855Sgabeblack@google.com * modification, are permitted provided that the following conditions are 712855Sgabeblack@google.com * met: redistributions of source code must retain the above copyright 812855Sgabeblack@google.com * notice, this list of conditions and the following disclaimer; 912855Sgabeblack@google.com * redistributions in binary form must reproduce the above copyright 1012855Sgabeblack@google.com * notice, this list of conditions and the following disclaimer in the 1112855Sgabeblack@google.com * documentation and/or other materials provided with the distribution; 1212855Sgabeblack@google.com * neither the name of the copyright holders nor the names of its 1312855Sgabeblack@google.com * contributors may be used to endorse or promote products derived from 1412855Sgabeblack@google.com * this software without specific prior written permission. 1512855Sgabeblack@google.com * 1612855Sgabeblack@google.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1712855Sgabeblack@google.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1812855Sgabeblack@google.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1912855Sgabeblack@google.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2012855Sgabeblack@google.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2112855Sgabeblack@google.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2212855Sgabeblack@google.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2312855Sgabeblack@google.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2412855Sgabeblack@google.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2512855Sgabeblack@google.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2612855Sgabeblack@google.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2712855Sgabeblack@google.com */ 2812855Sgabeblack@google.com 2912855Sgabeblack@google.com#include <string> 3012855Sgabeblack@google.com#include <vector> 3112855Sgabeblack@google.com 3212855Sgabeblack@google.com#include "cpu/base.hh" 3312855Sgabeblack@google.com#include "cpu/intr_control.hh" 3412855Sgabeblack@google.com#include "sim/builder.hh" 3512855Sgabeblack@google.com#include "sim/sim_object.hh" 3612855Sgabeblack@google.com 3712855Sgabeblack@google.comusing namespace std; 3812855Sgabeblack@google.com 3912855Sgabeblack@google.comIntrControl::IntrControl(const string &name, BaseCPU *c) 4012855Sgabeblack@google.com : SimObject(name), cpu(c) 4112855Sgabeblack@google.com{} 4212855Sgabeblack@google.com 4312855Sgabeblack@google.com/* @todo 4412855Sgabeblack@google.com *Fix the cpu sim object parameter to be a system pointer 4512855Sgabeblack@google.com *instead, to avoid some extra dereferencing 4612855Sgabeblack@google.com */ 4712855Sgabeblack@google.comvoid 4812855Sgabeblack@google.comIntrControl::post(int int_num, int index) 4912855Sgabeblack@google.com{ 5012855Sgabeblack@google.com std::vector<ExecContext *> &xcvec = cpu->system->execContexts; 5112855Sgabeblack@google.com BaseCPU *temp = xcvec[0]->cpu; 5212855Sgabeblack@google.com temp->post_interrupt(int_num, index); 5312855Sgabeblack@google.com} 5412855Sgabeblack@google.com 5512855Sgabeblack@google.comvoid 5612855Sgabeblack@google.comIntrControl::post(int cpu_id, int int_num, int index) 5712855Sgabeblack@google.com{ 5812855Sgabeblack@google.com std::vector<ExecContext *> &xcvec = cpu->system->execContexts; 5912855Sgabeblack@google.com BaseCPU *temp = xcvec[cpu_id]->cpu; 6012855Sgabeblack@google.com temp->post_interrupt(int_num, index); 6112855Sgabeblack@google.com} 6212855Sgabeblack@google.com 6312855Sgabeblack@google.comvoid 6412855Sgabeblack@google.comIntrControl::clear(int int_num, int index) 6512855Sgabeblack@google.com{ 6612855Sgabeblack@google.com std::vector<ExecContext *> &xcvec = cpu->system->execContexts; 6712855Sgabeblack@google.com BaseCPU *temp = xcvec[0]->cpu; 6812855Sgabeblack@google.com temp->clear_interrupt(int_num, index); 6912855Sgabeblack@google.com} 7012855Sgabeblack@google.com 7112855Sgabeblack@google.comvoid 7212855Sgabeblack@google.comIntrControl::clear(int cpu_id, int int_num, int index) 7312855Sgabeblack@google.com{ 7412855Sgabeblack@google.com std::vector<ExecContext *> &xcvec = cpu->system->execContexts; 7512855Sgabeblack@google.com BaseCPU *temp = xcvec[cpu_id]->cpu; 7612855Sgabeblack@google.com temp->clear_interrupt(int_num, index); 7712855Sgabeblack@google.com} 7812855Sgabeblack@google.com 7912855Sgabeblack@google.comBEGIN_DECLARE_SIM_OBJECT_PARAMS(IntrControl) 8012855Sgabeblack@google.com 8112855Sgabeblack@google.com SimObjectParam<BaseCPU *> cpu; 8212855Sgabeblack@google.com 8312855Sgabeblack@google.comEND_DECLARE_SIM_OBJECT_PARAMS(IntrControl) 8412855Sgabeblack@google.com 8512855Sgabeblack@google.comBEGIN_INIT_SIM_OBJECT_PARAMS(IntrControl) 8612855Sgabeblack@google.com 8712855Sgabeblack@google.com INIT_PARAM(cpu, "the cpu") 8812855Sgabeblack@google.com 8912855Sgabeblack@google.comEND_INIT_SIM_OBJECT_PARAMS(IntrControl) 9012855Sgabeblack@google.com 9112855Sgabeblack@google.comCREATE_SIM_OBJECT(IntrControl) 9212855Sgabeblack@google.com{ 9312855Sgabeblack@google.com return new IntrControl(getInstanceName(), cpu); 9412855Sgabeblack@google.com} 9512855Sgabeblack@google.com 9612855Sgabeblack@google.comREGISTER_SIM_OBJECT("IntrControl", IntrControl) 9712855Sgabeblack@google.com