thread_context.hh revision 8931:7a1dfb191e3f 
1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 */
42
43#ifndef __CPU_CHECKER_THREAD_CONTEXT_HH__
44#define __CPU_CHECKER_THREAD_CONTEXT_HH__
45
46#include "arch/types.hh"
47#include "config/the_isa.hh"
48#include "cpu/checker/cpu.hh"
49#include "cpu/simple_thread.hh"
50#include "cpu/thread_context.hh"
51#include "debug/Checker.hh"
52
53class EndQuiesceEvent;
54namespace TheISA {
55    namespace Kernel {
56        class Statistics;
57    };
58};
59
60/**
61 * Derived ThreadContext class for use with the Checker.  The template
62 * parameter is the ThreadContext class used by the specific CPU being
63 * verified.  This CheckerThreadContext is then used by the main CPU
64 * in place of its usual ThreadContext class.  It handles updating the
65 * checker's state any time state is updated externally through the
66 * ThreadContext.
67 */
68template <class TC>
69class CheckerThreadContext : public ThreadContext
70{
71  public:
72    CheckerThreadContext(TC *actual_tc,
73                         CheckerCPU *checker_cpu)
74        : actualTC(actual_tc), checkerTC(checker_cpu->thread),
75          checkerCPU(checker_cpu)
76    { }
77
78  private:
79    /** The main CPU's ThreadContext, or class that implements the
80     * ThreadContext interface. */
81    TC *actualTC;
82    /** The checker's own SimpleThread. Will be updated any time
83     * anything uses this ThreadContext to externally update a
84     * thread's state. */
85    SimpleThread *checkerTC;
86    /** Pointer to the checker CPU. */
87    CheckerCPU *checkerCPU;
88
89  public:
90
91    BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); }
92
93    int cpuId() { return actualTC->cpuId(); }
94
95    int contextId() { return actualTC->contextId(); }
96
97    void setContextId(int id)
98    {
99       actualTC->setContextId(id);
100       checkerTC->setContextId(id);
101    }
102
103    /** Returns this thread's ID number. */
104    int threadId() { return actualTC->threadId(); }
105    void setThreadId(int id)
106    {
107        checkerTC->setThreadId(id);
108        actualTC->setThreadId(id);
109    }
110
111    TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); }
112
113    TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); }
114
115    CheckerCPU *getCheckerCpuPtr()
116    {
117        return checkerCPU;
118    }
119
120    Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); }
121
122    System *getSystemPtr() { return actualTC->getSystemPtr(); }
123
124    TheISA::Kernel::Statistics *getKernelStats()
125    { return actualTC->getKernelStats(); }
126
127    Process *getProcessPtr() { return actualTC->getProcessPtr(); }
128
129    PortProxy &getPhysProxy() { return actualTC->getPhysProxy(); }
130
131    FSTranslatingPortProxy &getVirtProxy()
132    { return actualTC->getVirtProxy(); }
133
134    void initMemProxies(ThreadContext *tc)
135    { actualTC->initMemProxies(tc); }
136
137    void connectMemPorts(ThreadContext *tc)
138    {
139        actualTC->connectMemPorts(tc);
140    }
141
142    SETranslatingPortProxy &getMemProxy() { return actualTC->getMemProxy(); }
143
144    /** Executes a syscall in SE mode. */
145    void syscall(int64_t callnum)
146    { return actualTC->syscall(callnum); }
147
148    Status status() const { return actualTC->status(); }
149
150    void setStatus(Status new_status)
151    {
152        actualTC->setStatus(new_status);
153        checkerTC->setStatus(new_status);
154    }
155
156    /// Set the status to Active.  Optional delay indicates number of
157    /// cycles to wait before beginning execution.
158    void activate(int delay = 1) { actualTC->activate(delay); }
159
160    /// Set the status to Suspended.
161    void suspend(int delay) { actualTC->suspend(delay); }
162
163    /// Set the status to Halted.
164    void halt(int delay) { actualTC->halt(delay); }
165
166    void dumpFuncProfile() { actualTC->dumpFuncProfile(); }
167
168    void takeOverFrom(ThreadContext *oldContext)
169    {
170        actualTC->takeOverFrom(oldContext);
171        checkerTC->copyState(oldContext);
172    }
173
174    void regStats(const std::string &name)
175    {
176        actualTC->regStats(name);
177        checkerTC->regStats(name);
178    }
179
180    void serialize(std::ostream &os) { actualTC->serialize(os); }
181    void unserialize(Checkpoint *cp, const std::string &section)
182    { actualTC->unserialize(cp, section); }
183
184    EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); }
185
186    Tick readLastActivate() { return actualTC->readLastActivate(); }
187    Tick readLastSuspend() { return actualTC->readLastSuspend(); }
188
189    void profileClear() { return actualTC->profileClear(); }
190    void profileSample() { return actualTC->profileSample(); }
191
192    // @todo: Do I need this?
193    void copyArchRegs(ThreadContext *tc)
194    {
195        actualTC->copyArchRegs(tc);
196        checkerTC->copyArchRegs(tc);
197    }
198
199    void clearArchRegs()
200    {
201        actualTC->clearArchRegs();
202        checkerTC->clearArchRegs();
203    }
204
205    //
206    // New accessors for new decoder.
207    //
208    uint64_t readIntReg(int reg_idx)
209    { return actualTC->readIntReg(reg_idx); }
210
211    FloatReg readFloatReg(int reg_idx)
212    { return actualTC->readFloatReg(reg_idx); }
213
214    FloatRegBits readFloatRegBits(int reg_idx)
215    { return actualTC->readFloatRegBits(reg_idx); }
216
217    void setIntReg(int reg_idx, uint64_t val)
218    {
219        actualTC->setIntReg(reg_idx, val);
220        checkerTC->setIntReg(reg_idx, val);
221    }
222
223    void setFloatReg(int reg_idx, FloatReg val)
224    {
225        actualTC->setFloatReg(reg_idx, val);
226        checkerTC->setFloatReg(reg_idx, val);
227    }
228
229    void setFloatRegBits(int reg_idx, FloatRegBits val)
230    {
231        actualTC->setFloatRegBits(reg_idx, val);
232        checkerTC->setFloatRegBits(reg_idx, val);
233    }
234
235    /** Reads this thread's PC state. */
236    TheISA::PCState pcState()
237    { return actualTC->pcState(); }
238
239    /** Sets this thread's PC state. */
240    void pcState(const TheISA::PCState &val)
241    {
242        DPRINTF(Checker, "Changing PC to %s, old PC %s\n",
243                         val, checkerTC->pcState());
244        checkerTC->pcState(val);
245        checkerCPU->recordPCChange(val);
246        return actualTC->pcState(val);
247    }
248
249    void pcStateNoRecord(const TheISA::PCState &val)
250    {
251        return actualTC->pcState(val);
252    }
253
254    /** Reads this thread's PC. */
255    Addr instAddr()
256    { return actualTC->instAddr(); }
257
258    /** Reads this thread's next PC. */
259    Addr nextInstAddr()
260    { return actualTC->nextInstAddr(); }
261
262    /** Reads this thread's next PC. */
263    MicroPC microPC()
264    { return actualTC->microPC(); }
265
266    MiscReg readMiscRegNoEffect(int misc_reg)
267    { return actualTC->readMiscRegNoEffect(misc_reg); }
268
269    MiscReg readMiscReg(int misc_reg)
270    { return actualTC->readMiscReg(misc_reg); }
271
272    void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
273    {
274        DPRINTF(Checker, "Setting misc reg with no effect: %d to both Checker"
275                         " and O3..\n", misc_reg);
276        checkerTC->setMiscRegNoEffect(misc_reg, val);
277        actualTC->setMiscRegNoEffect(misc_reg, val);
278    }
279
280    void setMiscReg(int misc_reg, const MiscReg &val)
281    {
282        DPRINTF(Checker, "Setting misc reg with effect: %d to both Checker"
283                         " and O3..\n", misc_reg);
284        checkerTC->setMiscReg(misc_reg, val);
285        actualTC->setMiscReg(misc_reg, val);
286    }
287
288    int flattenIntIndex(int reg) { return actualTC->flattenIntIndex(reg); }
289    int flattenFloatIndex(int reg) { return actualTC->flattenFloatIndex(reg); }
290
291    unsigned readStCondFailures()
292    { return actualTC->readStCondFailures(); }
293
294    void setStCondFailures(unsigned sc_failures)
295    {
296        actualTC->setStCondFailures(sc_failures);
297    }
298
299    // @todo: Fix this!
300    bool misspeculating() { return actualTC->misspeculating(); }
301
302    Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
303};
304
305#endif // __CPU_CHECKER_EXEC_CONTEXT_HH__
306