thread_context.hh revision 8793:5f25086326ac
1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 */ 30 31#ifndef __CPU_CHECKER_THREAD_CONTEXT_HH__ 32#define __CPU_CHECKER_THREAD_CONTEXT_HH__ 33 34#include "arch/types.hh" 35#include "config/the_isa.hh" 36#include "cpu/checker/cpu.hh" 37#include "cpu/simple_thread.hh" 38#include "cpu/thread_context.hh" 39 40class EndQuiesceEvent; 41namespace TheISA { 42 namespace Kernel { 43 class Statistics; 44 }; 45}; 46 47/** 48 * Derived ThreadContext class for use with the Checker. The template 49 * parameter is the ThreadContext class used by the specific CPU being 50 * verified. This CheckerThreadContext is then used by the main CPU 51 * in place of its usual ThreadContext class. It handles updating the 52 * checker's state any time state is updated externally through the 53 * ThreadContext. 54 */ 55template <class TC> 56class CheckerThreadContext : public ThreadContext 57{ 58 public: 59 CheckerThreadContext(TC *actual_tc, 60 CheckerCPU *checker_cpu) 61 : actualTC(actual_tc), checkerTC(checker_cpu->thread), 62 checkerCPU(checker_cpu) 63 { } 64 65 private: 66 /** The main CPU's ThreadContext, or class that implements the 67 * ThreadContext interface. */ 68 TC *actualTC; 69 /** The checker's own SimpleThread. Will be updated any time 70 * anything uses this ThreadContext to externally update a 71 * thread's state. */ 72 SimpleThread *checkerTC; 73 /** Pointer to the checker CPU. */ 74 CheckerCPU *checkerCPU; 75 76 public: 77 78 BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); } 79 80 void setCpuId(int id) 81 { 82 actualTC->setCpuId(id); 83 checkerTC->setCpuId(id); 84 } 85 86 int cpuId() { return actualTC->cpuId(); } 87 88 TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); } 89 90 TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); } 91 92 System *getSystemPtr() { return actualTC->getSystemPtr(); } 93 94 PhysicalMemory *getPhysMemPtr() { return actualTC->getPhysMemPtr(); } 95 96 TheISA::Kernel::Statistics *getKernelStats() 97 { return actualTC->getKernelStats(); } 98 99 Process *getProcessPtr() { return actualTC->getProcessPtr(); } 100 101 TranslatingPort *getMemPort() { return actualTC->getMemPort(); } 102 103 VirtualPort *getVirtPort() 104 { return actualTC->getVirtPort(); } 105 106 FunctionalPort *getPhysPort() { return actualTC->getPhysPort(); } 107 108 Status status() const { return actualTC->status(); } 109 110 void setStatus(Status new_status) 111 { 112 actualTC->setStatus(new_status); 113 checkerTC->setStatus(new_status); 114 } 115 116 /// Set the status to Active. Optional delay indicates number of 117 /// cycles to wait before beginning execution. 118 void activate(int delay = 1) { actualTC->activate(delay); } 119 120 /// Set the status to Suspended. 121 void suspend() { actualTC->suspend(); } 122 123 /// Set the status to Halted. 124 void halt() { actualTC->halt(); } 125 126 void dumpFuncProfile() { actualTC->dumpFuncProfile(); } 127 128 void takeOverFrom(ThreadContext *oldContext) 129 { 130 actualTC->takeOverFrom(oldContext); 131 checkerTC->copyState(oldContext); 132 } 133 134 void regStats(const std::string &name) { actualTC->regStats(name); } 135 136 void serialize(std::ostream &os) { actualTC->serialize(os); } 137 void unserialize(Checkpoint *cp, const std::string §ion) 138 { actualTC->unserialize(cp, section); } 139 140 EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); } 141 142 Tick readLastActivate() { return actualTC->readLastActivate(); } 143 Tick readLastSuspend() { return actualTC->readLastSuspend(); } 144 145 void profileClear() { return actualTC->profileClear(); } 146 void profileSample() { return actualTC->profileSample(); } 147 148 int threadId() { return actualTC->threadId(); } 149 150 // @todo: Do I need this? 151 void copyArchRegs(ThreadContext *tc) 152 { 153 actualTC->copyArchRegs(tc); 154 checkerTC->copyArchRegs(tc); 155 } 156 157 void clearArchRegs() 158 { 159 actualTC->clearArchRegs(); 160 checkerTC->clearArchRegs(); 161 } 162 163 // 164 // New accessors for new decoder. 165 // 166 uint64_t readIntReg(int reg_idx) 167 { return actualTC->readIntReg(reg_idx); } 168 169 FloatReg readFloatReg(int reg_idx) 170 { return actualTC->readFloatReg(reg_idx); } 171 172 FloatRegBits readFloatRegBits(int reg_idx) 173 { return actualTC->readFloatRegBits(reg_idx); } 174 175 void setIntReg(int reg_idx, uint64_t val) 176 { 177 actualTC->setIntReg(reg_idx, val); 178 checkerTC->setIntReg(reg_idx, val); 179 } 180 181 void setFloatReg(int reg_idx, FloatReg val) 182 { 183 actualTC->setFloatReg(reg_idx, val); 184 checkerTC->setFloatReg(reg_idx, val); 185 } 186 187 void setFloatRegBits(int reg_idx, FloatRegBits val) 188 { 189 actualTC->setFloatRegBits(reg_idx, val); 190 checkerTC->setFloatRegBits(reg_idx, val); 191 } 192 193 uint64_t readPC() { return actualTC->readPC(); } 194 195 void setPC(uint64_t val) 196 { 197 actualTC->setPC(val); 198 checkerTC->setPC(val); 199 checkerCPU->recordPCChange(val); 200 } 201 202 uint64_t readNextPC() { return actualTC->readNextPC(); } 203 204 void setNextPC(uint64_t val) 205 { 206 actualTC->setNextPC(val); 207 checkerTC->setNextPC(val); 208 checkerCPU->recordNextPCChange(val); 209 } 210 211 uint64_t readNextNPC() { return actualTC->readNextNPC(); } 212 213 void setNextNPC(uint64_t val) 214 { 215 actualTC->setNextNPC(val); 216 checkerTC->setNextNPC(val); 217 checkerCPU->recordNextPCChange(val); 218 } 219 220 MiscReg readMiscRegNoEffect(int misc_reg) 221 { return actualTC->readMiscRegNoEffect(misc_reg); } 222 223 MiscReg readMiscReg(int misc_reg) 224 { return actualTC->readMiscReg(misc_reg); } 225 226 void setMiscRegNoEffect(int misc_reg, const MiscReg &val) 227 { 228 checkerTC->setMiscRegNoEffect(misc_reg, val); 229 actualTC->setMiscRegNoEffect(misc_reg, val); 230 } 231 232 void setMiscReg(int misc_reg, const MiscReg &val) 233 { 234 checkerTC->setMiscReg(misc_reg, val); 235 actualTC->setMiscReg(misc_reg, val); 236 } 237 238 unsigned readStCondFailures() 239 { return actualTC->readStCondFailures(); } 240 241 void setStCondFailures(unsigned sc_failures) 242 { 243 checkerTC->setStCondFailures(sc_failures); 244 actualTC->setStCondFailures(sc_failures); 245 } 246 247 // @todo: Fix this! 248 bool misspeculating() { return actualTC->misspeculating(); } 249 250 Counter readFuncExeInst() { return actualTC->readFuncExeInst(); } 251}; 252 253#endif // __CPU_CHECKER_EXEC_CONTEXT_HH__ 254