thread_context.hh revision 8733:64a7bf8fa56c
1/* 2 * Copyright (c) 2011 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2006 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Kevin Lim 41 */ 42 43#ifndef __CPU_CHECKER_THREAD_CONTEXT_HH__ 44#define __CPU_CHECKER_THREAD_CONTEXT_HH__ 45 46#include "arch/types.hh" 47#include "config/the_isa.hh" 48#include "cpu/checker/cpu.hh" 49#include "cpu/simple_thread.hh" 50#include "cpu/thread_context.hh" 51#include "debug/Checker.hh" 52 53class EndQuiesceEvent; 54namespace TheISA { 55 namespace Kernel { 56 class Statistics; 57 }; 58}; 59 60/** 61 * Derived ThreadContext class for use with the Checker. The template 62 * parameter is the ThreadContext class used by the specific CPU being 63 * verified. This CheckerThreadContext is then used by the main CPU 64 * in place of its usual ThreadContext class. It handles updating the 65 * checker's state any time state is updated externally through the 66 * ThreadContext. 67 */ 68template <class TC> 69class CheckerThreadContext : public ThreadContext 70{ 71 public: 72 CheckerThreadContext(TC *actual_tc, 73 CheckerCPU *checker_cpu) 74 : actualTC(actual_tc), checkerTC(checker_cpu->thread), 75 checkerCPU(checker_cpu) 76 { } 77 78 private: 79 /** The main CPU's ThreadContext, or class that implements the 80 * ThreadContext interface. */ 81 TC *actualTC; 82 /** The checker's own SimpleThread. Will be updated any time 83 * anything uses this ThreadContext to externally update a 84 * thread's state. */ 85 SimpleThread *checkerTC; 86 /** Pointer to the checker CPU. */ 87 CheckerCPU *checkerCPU; 88 89 public: 90 91 BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); } 92 93 int cpuId() { return actualTC->cpuId(); } 94 95 int contextId() { return actualTC->contextId(); } 96 97 void setContextId(int id) 98 { 99 actualTC->setContextId(id); 100 checkerTC->setContextId(id); 101 } 102 103 /** Returns this thread's ID number. */ 104 int threadId() { return actualTC->threadId(); } 105 void setThreadId(int id) 106 { 107 checkerTC->setThreadId(id); 108 actualTC->setThreadId(id); 109 } 110 111 TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); } 112 113 TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); } 114 115 BaseCPU *getCheckerCpuPtr() { return checkerTC->getCpuPtr(); } 116 117 Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); } 118 119 System *getSystemPtr() { return actualTC->getSystemPtr(); } 120 121#if FULL_SYSTEM 122 PhysicalMemory *getPhysMemPtr() { return actualTC->getPhysMemPtr(); } 123 124 TheISA::Kernel::Statistics *getKernelStats() 125 { return actualTC->getKernelStats(); } 126 127 PortProxy* getPhysProxy() { return actualTC->getPhysProxy(); } 128 129 FSTranslatingPortProxy* getVirtProxy() 130 { return actualTC->getVirtProxy(); } 131 132 //XXX: How does this work now? 133 void initMemProxies(ThreadContext *tc) 134 { actualTC->initMemProxies(tc); } 135 136 void connectMemPorts(ThreadContext *tc) 137 { 138 actualTC->connectMemPorts(tc); 139 } 140#else 141 SETranslatingPortProxy* getMemProxy() { return actualTC->getMemProxy(); } 142 143 Process *getProcessPtr() { return actualTC->getProcessPtr(); } 144 145 /** Executes a syscall in SE mode. */ 146 void syscall(int64_t callnum) 147 { return actualTC->syscall(callnum); } 148#endif 149 150 Status status() const { return actualTC->status(); } 151 152 void setStatus(Status new_status) 153 { 154 actualTC->setStatus(new_status); 155 checkerTC->setStatus(new_status); 156 } 157 158 /// Set the status to Active. Optional delay indicates number of 159 /// cycles to wait before beginning execution. 160 void activate(int delay = 1) { actualTC->activate(delay); } 161 162 /// Set the status to Suspended. 163 void suspend(int delay) { actualTC->suspend(delay); } 164 165 /// Set the status to Halted. 166 void halt(int delay) { actualTC->halt(delay); } 167 168#if FULL_SYSTEM 169 void dumpFuncProfile() { actualTC->dumpFuncProfile(); } 170#endif 171 172 void takeOverFrom(ThreadContext *oldContext) 173 { 174 actualTC->takeOverFrom(oldContext); 175 checkerTC->copyState(oldContext); 176 } 177 178 void regStats(const std::string &name) 179 { 180 actualTC->regStats(name); 181 checkerTC->regStats(name); 182 } 183 184 void serialize(std::ostream &os) { actualTC->serialize(os); } 185 void unserialize(Checkpoint *cp, const std::string §ion) 186 { actualTC->unserialize(cp, section); } 187 188#if FULL_SYSTEM 189 EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); } 190 191 Tick readLastActivate() { return actualTC->readLastActivate(); } 192 Tick readLastSuspend() { return actualTC->readLastSuspend(); } 193 194 void profileClear() { return actualTC->profileClear(); } 195 void profileSample() { return actualTC->profileSample(); } 196#endif 197 198 // @todo: Do I need this? 199 void copyArchRegs(ThreadContext *tc) 200 { 201 actualTC->copyArchRegs(tc); 202 checkerTC->copyArchRegs(tc); 203 } 204 205 void clearArchRegs() 206 { 207 actualTC->clearArchRegs(); 208 checkerTC->clearArchRegs(); 209 } 210 211 // 212 // New accessors for new decoder. 213 // 214 uint64_t readIntReg(int reg_idx) 215 { return actualTC->readIntReg(reg_idx); } 216 217 FloatReg readFloatReg(int reg_idx) 218 { return actualTC->readFloatReg(reg_idx); } 219 220 FloatRegBits readFloatRegBits(int reg_idx) 221 { return actualTC->readFloatRegBits(reg_idx); } 222 223 void setIntReg(int reg_idx, uint64_t val) 224 { 225 actualTC->setIntReg(reg_idx, val); 226 checkerTC->setIntReg(reg_idx, val); 227 } 228 229 void setFloatReg(int reg_idx, FloatReg val) 230 { 231 actualTC->setFloatReg(reg_idx, val); 232 checkerTC->setFloatReg(reg_idx, val); 233 } 234 235 void setFloatRegBits(int reg_idx, FloatRegBits val) 236 { 237 actualTC->setFloatRegBits(reg_idx, val); 238 checkerTC->setFloatRegBits(reg_idx, val); 239 } 240 241 /** Reads this thread's PC state. */ 242 TheISA::PCState pcState() 243 { return actualTC->pcState(); } 244 245 /** Sets this thread's PC state. */ 246 void pcState(const TheISA::PCState &val) 247 { 248 DPRINTF(Checker, "Changing PC to %s, old PC %s\n", 249 val, checkerTC->pcState()); 250 checkerTC->pcState(val); 251 checkerCPU->recordPCChange(val); 252 return actualTC->pcState(val); 253 } 254 255 void pcStateNoRecord(const TheISA::PCState &val) 256 { 257 return actualTC->pcState(val); 258 } 259 260 /** Reads this thread's PC. */ 261 Addr instAddr() 262 { return actualTC->instAddr(); } 263 264 /** Reads this thread's next PC. */ 265 Addr nextInstAddr() 266 { return actualTC->nextInstAddr(); } 267 268 /** Reads this thread's next PC. */ 269 MicroPC microPC() 270 { return actualTC->microPC(); } 271 272 MiscReg readMiscRegNoEffect(int misc_reg) 273 { return actualTC->readMiscRegNoEffect(misc_reg); } 274 275 MiscReg readMiscReg(int misc_reg) 276 { return actualTC->readMiscReg(misc_reg); } 277 278 void setMiscRegNoEffect(int misc_reg, const MiscReg &val) 279 { 280 DPRINTF(Checker, "Setting misc reg with no effect: %d to both Checker" 281 " and O3..\n", misc_reg); 282 checkerTC->setMiscRegNoEffect(misc_reg, val); 283 actualTC->setMiscRegNoEffect(misc_reg, val); 284 } 285 286 void setMiscReg(int misc_reg, const MiscReg &val) 287 { 288 DPRINTF(Checker, "Setting misc reg with effect: %d to both Checker" 289 " and O3..\n", misc_reg); 290 checkerTC->setMiscReg(misc_reg, val); 291 actualTC->setMiscReg(misc_reg, val); 292 } 293 294 int flattenIntIndex(int reg) { return actualTC->flattenIntIndex(reg); } 295 int flattenFloatIndex(int reg) { return actualTC->flattenFloatIndex(reg); } 296 297 unsigned readStCondFailures() 298 { return actualTC->readStCondFailures(); } 299 300 void setStCondFailures(unsigned sc_failures) 301 { 302 actualTC->setStCondFailures(sc_failures); 303 } 304 305 // @todo: Fix this! 306 bool misspeculating() { return actualTC->misspeculating(); } 307 308#if !FULL_SYSTEM 309 Counter readFuncExeInst() { return actualTC->readFuncExeInst(); } 310#endif 311}; 312 313#endif // __CPU_CHECKER_EXEC_CONTEXT_HH__ 314