thread_context.hh revision 3548
1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 */ 30 31#ifndef __CPU_CHECKER_THREAD_CONTEXT_HH__ 32#define __CPU_CHECKER_THREAD_CONTEXT_HH__ 33 34#include "arch/types.hh" 35#include "cpu/checker/cpu.hh" 36#include "cpu/simple_thread.hh" 37#include "cpu/thread_context.hh" 38 39class EndQuiesceEvent; 40namespace TheISA { 41 namespace Kernel { 42 class Statistics; 43 }; 44}; 45 46/** 47 * Derived ThreadContext class for use with the Checker. The template 48 * parameter is the ThreadContext class used by the specific CPU being 49 * verified. This CheckerThreadContext is then used by the main CPU 50 * in place of its usual ThreadContext class. It handles updating the 51 * checker's state any time state is updated externally through the 52 * ThreadContext. 53 */ 54template <class TC> 55class CheckerThreadContext : public ThreadContext 56{ 57 public: 58 CheckerThreadContext(TC *actual_tc, 59 CheckerCPU *checker_cpu) 60 : actualTC(actual_tc), checkerTC(checker_cpu->thread), 61 checkerCPU(checker_cpu) 62 { } 63 64 private: 65 /** The main CPU's ThreadContext, or class that implements the 66 * ThreadContext interface. */ 67 TC *actualTC; 68 /** The checker's own SimpleThread. Will be updated any time 69 * anything uses this ThreadContext to externally update a 70 * thread's state. */ 71 SimpleThread *checkerTC; 72 /** Pointer to the checker CPU. */ 73 CheckerCPU *checkerCPU; 74 75 public: 76 77 BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); } 78 79 void setCpuId(int id) 80 { 81 actualTC->setCpuId(id); 82 checkerTC->setCpuId(id); 83 } 84 85 int readCpuId() { return actualTC->readCpuId(); } 86 87#if FULL_SYSTEM 88 System *getSystemPtr() { return actualTC->getSystemPtr(); } 89 90 PhysicalMemory *getPhysMemPtr() { return actualTC->getPhysMemPtr(); } 91 92 TheISA::ITB *getITBPtr() { return actualTC->getITBPtr(); } 93 94 TheISA::DTB *getDTBPtr() { return actualTC->getDTBPtr(); } 95 96 TheISA::Kernel::Statistics *getKernelStats() 97 { return actualTC->getKernelStats(); } 98 99 FunctionalPort *getPhysPort() { return actualTC->getPhysPort(); } 100 101 VirtualPort *getVirtPort(ThreadContext *tc = NULL) 102 { return actualTC->getVirtPort(); } 103 104 void delVirtPort(VirtualPort *vp) { actualTC->delVirtPort(vp); } 105#else 106 TranslatingPort *getMemPort() { return actualTC->getMemPort(); } 107 108 Process *getProcessPtr() { return actualTC->getProcessPtr(); } 109#endif 110 111 Status status() const { return actualTC->status(); } 112 113 void setStatus(Status new_status) 114 { 115 actualTC->setStatus(new_status); 116 checkerTC->setStatus(new_status); 117 } 118 119 /// Set the status to Active. Optional delay indicates number of 120 /// cycles to wait before beginning execution. 121 void activate(int delay = 1) { actualTC->activate(delay); } 122 123 /// Set the status to Suspended. 124 void suspend() { actualTC->suspend(); } 125 126 /// Set the status to Unallocated. 127 void deallocate(int delay = 0) { actualTC->deallocate(delay); } 128 129 /// Set the status to Halted. 130 void halt() { actualTC->halt(); } 131 132#if FULL_SYSTEM 133 void dumpFuncProfile() { actualTC->dumpFuncProfile(); } 134#endif 135 136 void takeOverFrom(ThreadContext *oldContext) 137 { 138 actualTC->takeOverFrom(oldContext); 139 checkerTC->copyState(oldContext); 140 } 141 142 void regStats(const std::string &name) { actualTC->regStats(name); } 143 144 void serialize(std::ostream &os) { actualTC->serialize(os); } 145 void unserialize(Checkpoint *cp, const std::string §ion) 146 { actualTC->unserialize(cp, section); } 147 148#if FULL_SYSTEM 149 EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); } 150 151 Tick readLastActivate() { return actualTC->readLastActivate(); } 152 Tick readLastSuspend() { return actualTC->readLastSuspend(); } 153 154 void profileClear() { return actualTC->profileClear(); } 155 void profileSample() { return actualTC->profileSample(); } 156#endif 157 158 int getThreadNum() { return actualTC->getThreadNum(); } 159 160 // @todo: Do I need this? 161 MachInst getInst() { return actualTC->getInst(); } 162 163 // @todo: Do I need this? 164 void copyArchRegs(ThreadContext *tc) 165 { 166 actualTC->copyArchRegs(tc); 167 checkerTC->copyArchRegs(tc); 168 } 169 170 void clearArchRegs() 171 { 172 actualTC->clearArchRegs(); 173 checkerTC->clearArchRegs(); 174 } 175 176 // 177 // New accessors for new decoder. 178 // 179 uint64_t readIntReg(int reg_idx) 180 { return actualTC->readIntReg(reg_idx); } 181 182 FloatReg readFloatReg(int reg_idx, int width) 183 { return actualTC->readFloatReg(reg_idx, width); } 184 185 FloatReg readFloatReg(int reg_idx) 186 { return actualTC->readFloatReg(reg_idx); } 187 188 FloatRegBits readFloatRegBits(int reg_idx, int width) 189 { return actualTC->readFloatRegBits(reg_idx, width); } 190 191 FloatRegBits readFloatRegBits(int reg_idx) 192 { return actualTC->readFloatRegBits(reg_idx); } 193 194 void setIntReg(int reg_idx, uint64_t val) 195 { 196 actualTC->setIntReg(reg_idx, val); 197 checkerTC->setIntReg(reg_idx, val); 198 } 199 200 void setFloatReg(int reg_idx, FloatReg val, int width) 201 { 202 actualTC->setFloatReg(reg_idx, val, width); 203 checkerTC->setFloatReg(reg_idx, val, width); 204 } 205 206 void setFloatReg(int reg_idx, FloatReg val) 207 { 208 actualTC->setFloatReg(reg_idx, val); 209 checkerTC->setFloatReg(reg_idx, val); 210 } 211 212 void setFloatRegBits(int reg_idx, FloatRegBits val, int width) 213 { 214 actualTC->setFloatRegBits(reg_idx, val, width); 215 checkerTC->setFloatRegBits(reg_idx, val, width); 216 } 217 218 void setFloatRegBits(int reg_idx, FloatRegBits val) 219 { 220 actualTC->setFloatRegBits(reg_idx, val); 221 checkerTC->setFloatRegBits(reg_idx, val); 222 } 223 224 uint64_t readPC() { return actualTC->readPC(); } 225 226 void setPC(uint64_t val) 227 { 228 actualTC->setPC(val); 229 checkerTC->setPC(val); 230 checkerCPU->recordPCChange(val); 231 } 232 233 uint64_t readNextPC() { return actualTC->readNextPC(); } 234 235 void setNextPC(uint64_t val) 236 { 237 actualTC->setNextPC(val); 238 checkerTC->setNextPC(val); 239 checkerCPU->recordNextPCChange(val); 240 } 241 242 uint64_t readNextNPC() { return actualTC->readNextNPC(); } 243 244 void setNextNPC(uint64_t val) 245 { 246 actualTC->setNextNPC(val); 247 checkerTC->setNextNPC(val); 248 checkerCPU->recordNextPCChange(val); 249 } 250 251 MiscReg readMiscReg(int misc_reg) 252 { return actualTC->readMiscReg(misc_reg); } 253 254 MiscReg readMiscRegWithEffect(int misc_reg) 255 { return actualTC->readMiscRegWithEffect(misc_reg); } 256 257 void setMiscReg(int misc_reg, const MiscReg &val) 258 { 259 checkerTC->setMiscReg(misc_reg, val); 260 actualTC->setMiscReg(misc_reg, val); 261 } 262 263 void setMiscRegWithEffect(int misc_reg, const MiscReg &val) 264 { 265 checkerTC->setMiscRegWithEffect(misc_reg, val); 266 actualTC->setMiscRegWithEffect(misc_reg, val); 267 } 268 269 unsigned readStCondFailures() 270 { return actualTC->readStCondFailures(); } 271 272 void setStCondFailures(unsigned sc_failures) 273 { 274 checkerTC->setStCondFailures(sc_failures); 275 actualTC->setStCondFailures(sc_failures); 276 } 277 278 // @todo: Fix this! 279 bool misspeculating() { return actualTC->misspeculating(); } 280 281#if !FULL_SYSTEM 282 IntReg getSyscallArg(int i) { return actualTC->getSyscallArg(i); } 283 284 // used to shift args for indirect syscall 285 void setSyscallArg(int i, IntReg val) 286 { 287 checkerTC->setSyscallArg(i, val); 288 actualTC->setSyscallArg(i, val); 289 } 290 291 void setSyscallReturn(SyscallReturn return_value) 292 { 293 checkerTC->setSyscallReturn(return_value); 294 actualTC->setSyscallReturn(return_value); 295 } 296 297 Counter readFuncExeInst() { return actualTC->readFuncExeInst(); } 298#endif 299 void changeRegFileContext(TheISA::RegContextParam param, 300 TheISA::RegContextVal val) 301 { 302 actualTC->changeRegFileContext(param, val); 303 checkerTC->changeRegFileContext(param, val); 304 } 305}; 306 307#endif // __CPU_CHECKER_EXEC_CONTEXT_HH__ 308