thread_context.hh revision 13628:332f730a1855
1/* 2 * Copyright (c) 2011-2012, 2016-2018 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * 15 * Copyright (c) 2006 The Regents of The University of Michigan 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Kevin Lim 42 */ 43 44#ifndef __CPU_CHECKER_THREAD_CONTEXT_HH__ 45#define __CPU_CHECKER_THREAD_CONTEXT_HH__ 46 47#include "arch/types.hh" 48#include "config/the_isa.hh" 49#include "cpu/checker/cpu.hh" 50#include "cpu/simple_thread.hh" 51#include "cpu/thread_context.hh" 52#include "debug/Checker.hh" 53 54class EndQuiesceEvent; 55namespace TheISA { 56 namespace Kernel { 57 class Statistics; 58 }; 59 class Decoder; 60}; 61 62/** 63 * Derived ThreadContext class for use with the Checker. The template 64 * parameter is the ThreadContext class used by the specific CPU being 65 * verified. This CheckerThreadContext is then used by the main CPU 66 * in place of its usual ThreadContext class. It handles updating the 67 * checker's state any time state is updated externally through the 68 * ThreadContext. 69 */ 70template <class TC> 71class CheckerThreadContext : public ThreadContext 72{ 73 public: 74 CheckerThreadContext(TC *actual_tc, 75 CheckerCPU *checker_cpu) 76 : actualTC(actual_tc), checkerTC(checker_cpu->thread), 77 checkerCPU(checker_cpu) 78 { } 79 80 private: 81 /** The main CPU's ThreadContext, or class that implements the 82 * ThreadContext interface. */ 83 TC *actualTC; 84 /** The checker's own SimpleThread. Will be updated any time 85 * anything uses this ThreadContext to externally update a 86 * thread's state. */ 87 SimpleThread *checkerTC; 88 /** Pointer to the checker CPU. */ 89 CheckerCPU *checkerCPU; 90 91 public: 92 93 BaseCPU *getCpuPtr() override { return actualTC->getCpuPtr(); } 94 95 uint32_t socketId() const override { return actualTC->socketId(); } 96 97 int cpuId() const override { return actualTC->cpuId(); } 98 99 ContextID contextId() const override { return actualTC->contextId(); } 100 101 void setContextId(ContextID id)override 102 { 103 actualTC->setContextId(id); 104 checkerTC->setContextId(id); 105 } 106 107 /** Returns this thread's ID number. */ 108 int threadId() const override { return actualTC->threadId(); } 109 void setThreadId(int id) override 110 { 111 checkerTC->setThreadId(id); 112 actualTC->setThreadId(id); 113 } 114 115 BaseTLB *getITBPtr() override { return actualTC->getITBPtr(); } 116 117 BaseTLB *getDTBPtr() override { return actualTC->getDTBPtr(); } 118 119 CheckerCPU *getCheckerCpuPtr()override 120 { 121 return checkerCPU; 122 } 123 124 TheISA::Decoder *getDecoderPtr() override { 125 return actualTC->getDecoderPtr(); 126 } 127 128 System *getSystemPtr() override { return actualTC->getSystemPtr(); } 129 130 TheISA::Kernel::Statistics *getKernelStats()override 131 { return actualTC->getKernelStats(); } 132 133 Process *getProcessPtr() override { return actualTC->getProcessPtr(); } 134 135 void setProcessPtr(Process *p) override { actualTC->setProcessPtr(p); } 136 137 PortProxy &getPhysProxy() override { return actualTC->getPhysProxy(); } 138 139 FSTranslatingPortProxy &getVirtProxy() override 140 { return actualTC->getVirtProxy(); } 141 142 void initMemProxies(ThreadContext *tc) override 143 { actualTC->initMemProxies(tc); } 144 145 void connectMemPorts(ThreadContext *tc) 146 { 147 actualTC->connectMemPorts(tc); 148 } 149 150 SETranslatingPortProxy &getMemProxy() override { 151 return actualTC->getMemProxy(); 152 } 153 154 /** Executes a syscall in SE mode. */ 155 void syscall(int64_t callnum, Fault *fault)override 156 { return actualTC->syscall(callnum, fault); } 157 158 Status status() const override { return actualTC->status(); } 159 160 void setStatus(Status new_status) override 161 { 162 actualTC->setStatus(new_status); 163 checkerTC->setStatus(new_status); 164 } 165 166 /// Set the status to Active. 167 void activate() override { actualTC->activate(); } 168 169 /// Set the status to Suspended. 170 void suspend() override{ actualTC->suspend(); } 171 172 /// Set the status to Halted. 173 void halt() override{ actualTC->halt(); } 174 175 void dumpFuncProfile() override{ actualTC->dumpFuncProfile(); } 176 177 void takeOverFrom(ThreadContext *oldContext) override 178 { 179 actualTC->takeOverFrom(oldContext); 180 checkerTC->copyState(oldContext); 181 } 182 183 void regStats(const std::string &name) override 184 { 185 actualTC->regStats(name); 186 checkerTC->regStats(name); 187 } 188 189 EndQuiesceEvent *getQuiesceEvent() override { 190 return actualTC->getQuiesceEvent(); 191 } 192 193 Tick readLastActivate() override{ return actualTC->readLastActivate(); } 194 Tick readLastSuspend() override{ return actualTC->readLastSuspend(); } 195 196 void profileClear() override{ return actualTC->profileClear(); } 197 void profileSample() override{ return actualTC->profileSample(); } 198 199 // @todo: Do I need this? 200 void copyArchRegs(ThreadContext *tc) override 201 { 202 actualTC->copyArchRegs(tc); 203 checkerTC->copyArchRegs(tc); 204 } 205 206 void clearArchRegs() override 207 { 208 actualTC->clearArchRegs(); 209 checkerTC->clearArchRegs(); 210 } 211 212 // 213 // New accessors for new decoder. 214 // 215 RegVal readIntReg(int reg_idx) override { 216 return actualTC->readIntReg(reg_idx); 217 } 218 219 RegVal 220 readFloatReg(int reg_idx) override 221 { 222 return actualTC->readFloatReg(reg_idx); 223 } 224 225 const VecRegContainer& readVecReg (const RegId& reg) const override 226 { return actualTC->readVecReg(reg); } 227 228 /** 229 * Read vector register for modification, hierarchical indexing. 230 */ 231 VecRegContainer& getWritableVecReg (const RegId& reg) override 232 { return actualTC->getWritableVecReg(reg); } 233 234 /** Vector Register Lane Interfaces. */ 235 /** @{ */ 236 /** Reads source vector 8bit operand. */ 237 ConstVecLane8 238 readVec8BitLaneReg(const RegId& reg) const override 239 { return actualTC->readVec8BitLaneReg(reg); } 240 241 /** Reads source vector 16bit operand. */ 242 ConstVecLane16 243 readVec16BitLaneReg(const RegId& reg) const override 244 { return actualTC->readVec16BitLaneReg(reg); } 245 246 /** Reads source vector 32bit operand. */ 247 ConstVecLane32 248 readVec32BitLaneReg(const RegId& reg) const override 249 { return actualTC->readVec32BitLaneReg(reg); } 250 251 /** Reads source vector 64bit operand. */ 252 ConstVecLane64 253 readVec64BitLaneReg(const RegId& reg) const override 254 { return actualTC->readVec64BitLaneReg(reg); } 255 256 /** Write a lane of the destination vector register. */ 257 virtual void setVecLane(const RegId& reg, 258 const LaneData<LaneSize::Byte>& val) override 259 { return actualTC->setVecLane(reg, val); } 260 virtual void setVecLane(const RegId& reg, 261 const LaneData<LaneSize::TwoByte>& val) override 262 { return actualTC->setVecLane(reg, val); } 263 virtual void setVecLane(const RegId& reg, 264 const LaneData<LaneSize::FourByte>& val) override 265 { return actualTC->setVecLane(reg, val); } 266 virtual void setVecLane(const RegId& reg, 267 const LaneData<LaneSize::EightByte>& val) override 268 { return actualTC->setVecLane(reg, val); } 269 /** @} */ 270 271 const VecElem& readVecElem(const RegId& reg) const override 272 { return actualTC->readVecElem(reg); } 273 274 const VecPredRegContainer& readVecPredReg(const RegId& reg) const override 275 { return actualTC->readVecPredReg(reg); } 276 277 VecPredRegContainer& getWritableVecPredReg(const RegId& reg) override 278 { return actualTC->getWritableVecPredReg(reg); } 279 280 RegVal readCCReg(int reg_idx) override 281 { return actualTC->readCCReg(reg_idx); } 282 283 void 284 setIntReg(int reg_idx, RegVal val) override 285 { 286 actualTC->setIntReg(reg_idx, val); 287 checkerTC->setIntReg(reg_idx, val); 288 } 289 290 void 291 setFloatReg(int reg_idx, RegVal val) override 292 { 293 actualTC->setFloatReg(reg_idx, val); 294 checkerTC->setFloatReg(reg_idx, val); 295 } 296 297 void 298 setVecReg(const RegId& reg, const VecRegContainer& val) override 299 { 300 actualTC->setVecReg(reg, val); 301 checkerTC->setVecReg(reg, val); 302 } 303 304 void 305 setVecElem(const RegId& reg, const VecElem& val) override 306 { 307 actualTC->setVecElem(reg, val); 308 checkerTC->setVecElem(reg, val); 309 } 310 311 void 312 setVecPredReg(const RegId& reg, const VecPredRegContainer& val) override 313 { 314 actualTC->setVecPredReg(reg, val); 315 checkerTC->setVecPredReg(reg, val); 316 } 317 318 void 319 setCCReg(int reg_idx, RegVal val) override 320 { 321 actualTC->setCCReg(reg_idx, val); 322 checkerTC->setCCReg(reg_idx, val); 323 } 324 325 /** Reads this thread's PC state. */ 326 TheISA::PCState pcState() override 327 { return actualTC->pcState(); } 328 329 /** Sets this thread's PC state. */ 330 void 331 pcState(const TheISA::PCState &val) override 332 { 333 DPRINTF(Checker, "Changing PC to %s, old PC %s\n", 334 val, checkerTC->pcState()); 335 checkerTC->pcState(val); 336 checkerCPU->recordPCChange(val); 337 return actualTC->pcState(val); 338 } 339 340 void 341 setNPC(Addr val) 342 { 343 checkerTC->setNPC(val); 344 actualTC->setNPC(val); 345 } 346 347 void 348 pcStateNoRecord(const TheISA::PCState &val) override 349 { 350 return actualTC->pcState(val); 351 } 352 353 /** Reads this thread's PC. */ 354 Addr instAddr() override 355 { return actualTC->instAddr(); } 356 357 /** Reads this thread's next PC. */ 358 Addr nextInstAddr() override 359 { return actualTC->nextInstAddr(); } 360 361 /** Reads this thread's next PC. */ 362 MicroPC microPC() override 363 { return actualTC->microPC(); } 364 365 RegVal readMiscRegNoEffect(int misc_reg) const override 366 { return actualTC->readMiscRegNoEffect(misc_reg); } 367 368 RegVal readMiscReg(int misc_reg) override 369 { return actualTC->readMiscReg(misc_reg); } 370 371 void 372 setMiscRegNoEffect(int misc_reg, RegVal val) override 373 { 374 DPRINTF(Checker, "Setting misc reg with no effect: %d to both Checker" 375 " and O3..\n", misc_reg); 376 checkerTC->setMiscRegNoEffect(misc_reg, val); 377 actualTC->setMiscRegNoEffect(misc_reg, val); 378 } 379 380 void 381 setMiscReg(int misc_reg, RegVal val) override 382 { 383 DPRINTF(Checker, "Setting misc reg with effect: %d to both Checker" 384 " and O3..\n", misc_reg); 385 checkerTC->setMiscReg(misc_reg, val); 386 actualTC->setMiscReg(misc_reg, val); 387 } 388 389 RegId 390 flattenRegId(const RegId& regId) const override 391 { 392 return actualTC->flattenRegId(regId); 393 } 394 395 unsigned readStCondFailures() override 396 { return actualTC->readStCondFailures(); } 397 398 void 399 setStCondFailures(unsigned sc_failures) override 400 { 401 actualTC->setStCondFailures(sc_failures); 402 } 403 404 Counter readFuncExeInst() override { return actualTC->readFuncExeInst(); } 405 406 RegVal readIntRegFlat(int idx) override { 407 return actualTC->readIntRegFlat(idx); 408 } 409 410 void 411 setIntRegFlat(int idx, RegVal val) override 412 { 413 actualTC->setIntRegFlat(idx, val); 414 } 415 416 RegVal 417 readFloatRegFlat(int idx) override 418 { 419 return actualTC->readFloatRegFlat(idx); 420 } 421 422 void 423 setFloatRegFlat(int idx, RegVal val) override 424 { 425 actualTC->setFloatRegFlat(idx, val); 426 } 427 428 const VecRegContainer & 429 readVecRegFlat(int idx) const override 430 { 431 return actualTC->readVecRegFlat(idx); 432 } 433 434 /** 435 * Read vector register for modification, flat indexing. 436 */ 437 VecRegContainer & 438 getWritableVecRegFlat(int idx) override 439 { 440 return actualTC->getWritableVecRegFlat(idx); 441 } 442 443 void setVecRegFlat(int idx, const VecRegContainer& val) override 444 { actualTC->setVecRegFlat(idx, val); } 445 446 const VecElem& readVecElemFlat(const RegIndex& idx, 447 const ElemIndex& elem_idx) const override 448 { return actualTC->readVecElemFlat(idx, elem_idx); } 449 450 void setVecElemFlat(const RegIndex& idx, 451 const ElemIndex& elem_idx, const VecElem& val) override 452 { actualTC->setVecElemFlat(idx, elem_idx, val); } 453 454 const VecPredRegContainer& readVecPredRegFlat(int idx) const override 455 { return actualTC->readVecPredRegFlat(idx); } 456 457 VecPredRegContainer& getWritableVecPredRegFlat(int idx) override 458 { return actualTC->getWritableVecPredRegFlat(idx); } 459 460 void setVecPredRegFlat(int idx, const VecPredRegContainer& val) override 461 { actualTC->setVecPredRegFlat(idx, val); } 462 463 RegVal readCCRegFlat(int idx) override 464 { return actualTC->readCCRegFlat(idx); } 465 466 void setCCRegFlat(int idx, RegVal val) override 467 { actualTC->setCCRegFlat(idx, val); } 468}; 469 470#endif // __CPU_CHECKER_EXEC_CONTEXT_HH__ 471