thread_context.hh revision 13611:c8b7847b4171 
1/*
2 * Copyright (c) 2011-2012, 2016-2018 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder.  You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 */
43
44#ifndef __CPU_CHECKER_THREAD_CONTEXT_HH__
45#define __CPU_CHECKER_THREAD_CONTEXT_HH__
46
47#include "arch/types.hh"
48#include "config/the_isa.hh"
49#include "cpu/checker/cpu.hh"
50#include "cpu/simple_thread.hh"
51#include "cpu/thread_context.hh"
52#include "debug/Checker.hh"
53
54class EndQuiesceEvent;
55namespace TheISA {
56    namespace Kernel {
57        class Statistics;
58    };
59    class Decoder;
60};
61
62/**
63 * Derived ThreadContext class for use with the Checker.  The template
64 * parameter is the ThreadContext class used by the specific CPU being
65 * verified.  This CheckerThreadContext is then used by the main CPU
66 * in place of its usual ThreadContext class.  It handles updating the
67 * checker's state any time state is updated externally through the
68 * ThreadContext.
69 */
70template <class TC>
71class CheckerThreadContext : public ThreadContext
72{
73  public:
74    CheckerThreadContext(TC *actual_tc,
75                         CheckerCPU *checker_cpu)
76        : actualTC(actual_tc), checkerTC(checker_cpu->thread),
77          checkerCPU(checker_cpu)
78    { }
79
80  private:
81    /** The main CPU's ThreadContext, or class that implements the
82     * ThreadContext interface. */
83    TC *actualTC;
84    /** The checker's own SimpleThread. Will be updated any time
85     * anything uses this ThreadContext to externally update a
86     * thread's state. */
87    SimpleThread *checkerTC;
88    /** Pointer to the checker CPU. */
89    CheckerCPU *checkerCPU;
90
91  public:
92
93    BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); }
94
95    uint32_t socketId() const { return actualTC->socketId(); }
96
97    int cpuId() const { return actualTC->cpuId(); }
98
99    ContextID contextId() const { return actualTC->contextId(); }
100
101    void setContextId(ContextID id)
102    {
103       actualTC->setContextId(id);
104       checkerTC->setContextId(id);
105    }
106
107    /** Returns this thread's ID number. */
108    int threadId() const { return actualTC->threadId(); }
109    void setThreadId(int id)
110    {
111        checkerTC->setThreadId(id);
112        actualTC->setThreadId(id);
113    }
114
115    BaseTLB *getITBPtr() { return actualTC->getITBPtr(); }
116
117    BaseTLB *getDTBPtr() { return actualTC->getDTBPtr(); }
118
119    CheckerCPU *getCheckerCpuPtr()
120    {
121        return checkerCPU;
122    }
123
124    TheISA::Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); }
125
126    System *getSystemPtr() { return actualTC->getSystemPtr(); }
127
128    TheISA::Kernel::Statistics *getKernelStats()
129    { return actualTC->getKernelStats(); }
130
131    Process *getProcessPtr() { return actualTC->getProcessPtr(); }
132
133    void setProcessPtr(Process *p) { actualTC->setProcessPtr(p); }
134
135    PortProxy &getPhysProxy() { return actualTC->getPhysProxy(); }
136
137    FSTranslatingPortProxy &getVirtProxy()
138    { return actualTC->getVirtProxy(); }
139
140    void initMemProxies(ThreadContext *tc)
141    { actualTC->initMemProxies(tc); }
142
143    void connectMemPorts(ThreadContext *tc)
144    {
145        actualTC->connectMemPorts(tc);
146    }
147
148    SETranslatingPortProxy &getMemProxy() { return actualTC->getMemProxy(); }
149
150    /** Executes a syscall in SE mode. */
151    void syscall(int64_t callnum, Fault *fault)
152    { return actualTC->syscall(callnum, fault); }
153
154    Status status() const { return actualTC->status(); }
155
156    void setStatus(Status new_status)
157    {
158        actualTC->setStatus(new_status);
159        checkerTC->setStatus(new_status);
160    }
161
162    /// Set the status to Active.
163    void activate() { actualTC->activate(); }
164
165    /// Set the status to Suspended.
166    void suspend() { actualTC->suspend(); }
167
168    /// Set the status to Halted.
169    void halt() { actualTC->halt(); }
170
171    void dumpFuncProfile() { actualTC->dumpFuncProfile(); }
172
173    void takeOverFrom(ThreadContext *oldContext)
174    {
175        actualTC->takeOverFrom(oldContext);
176        checkerTC->copyState(oldContext);
177    }
178
179    void regStats(const std::string &name)
180    {
181        actualTC->regStats(name);
182        checkerTC->regStats(name);
183    }
184
185    EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); }
186
187    Tick readLastActivate() { return actualTC->readLastActivate(); }
188    Tick readLastSuspend() { return actualTC->readLastSuspend(); }
189
190    void profileClear() { return actualTC->profileClear(); }
191    void profileSample() { return actualTC->profileSample(); }
192
193    // @todo: Do I need this?
194    void copyArchRegs(ThreadContext *tc)
195    {
196        actualTC->copyArchRegs(tc);
197        checkerTC->copyArchRegs(tc);
198    }
199
200    void clearArchRegs()
201    {
202        actualTC->clearArchRegs();
203        checkerTC->clearArchRegs();
204    }
205
206    //
207    // New accessors for new decoder.
208    //
209    RegVal readIntReg(int reg_idx) { return actualTC->readIntReg(reg_idx); }
210
211    RegVal
212    readFloatReg(int reg_idx)
213    {
214        return actualTC->readFloatReg(reg_idx);
215    }
216
217    const VecRegContainer& readVecReg(const RegId& reg) const
218    { return actualTC->readVecReg(reg); }
219
220    /**
221     * Read vector register for modification, hierarchical indexing.
222     */
223    VecRegContainer& getWritableVecReg(const RegId& reg)
224    { return actualTC->getWritableVecReg(reg); }
225
226    /** Vector Register Lane Interfaces. */
227    /** @{ */
228    /** Reads source vector 8bit operand. */
229    ConstVecLane8
230    readVec8BitLaneReg(const RegId& reg) const
231    { return actualTC->readVec8BitLaneReg(reg); }
232
233    /** Reads source vector 16bit operand. */
234    ConstVecLane16
235    readVec16BitLaneReg(const RegId& reg) const
236    { return actualTC->readVec16BitLaneReg(reg); }
237
238    /** Reads source vector 32bit operand. */
239    ConstVecLane32
240    readVec32BitLaneReg(const RegId& reg) const
241    { return actualTC->readVec32BitLaneReg(reg); }
242
243    /** Reads source vector 64bit operand. */
244    ConstVecLane64
245    readVec64BitLaneReg(const RegId& reg) const
246    { return actualTC->readVec64BitLaneReg(reg); }
247
248    /** Write a lane of the destination vector register. */
249    virtual void setVecLane(const RegId& reg,
250            const LaneData<LaneSize::Byte>& val)
251    { return actualTC->setVecLane(reg, val); }
252    virtual void setVecLane(const RegId& reg,
253            const LaneData<LaneSize::TwoByte>& val)
254    { return actualTC->setVecLane(reg, val); }
255    virtual void setVecLane(const RegId& reg,
256            const LaneData<LaneSize::FourByte>& val)
257    { return actualTC->setVecLane(reg, val); }
258    virtual void setVecLane(const RegId& reg,
259            const LaneData<LaneSize::EightByte>& val)
260    { return actualTC->setVecLane(reg, val); }
261    /** @} */
262
263    const VecElem& readVecElem(const RegId& reg) const
264    { return actualTC->readVecElem(reg); }
265
266    const VecPredRegContainer& readVecPredReg(const RegId& reg) const override
267    { return actualTC->readVecPredReg(reg); }
268
269    VecPredRegContainer& getWritableVecPredReg(const RegId& reg) override
270    { return actualTC->getWritableVecPredReg(reg); }
271
272    CCReg readCCReg(int reg_idx)
273    { return actualTC->readCCReg(reg_idx); }
274
275    void
276    setIntReg(int reg_idx, RegVal val)
277    {
278        actualTC->setIntReg(reg_idx, val);
279        checkerTC->setIntReg(reg_idx, val);
280    }
281
282    void
283    setFloatReg(int reg_idx, RegVal val)
284    {
285        actualTC->setFloatReg(reg_idx, val);
286        checkerTC->setFloatReg(reg_idx, val);
287    }
288
289    void
290    setVecReg(const RegId& reg, const VecRegContainer& val)
291    {
292        actualTC->setVecReg(reg, val);
293        checkerTC->setVecReg(reg, val);
294    }
295
296    void
297    setVecElem(const RegId& reg, const VecElem& val)
298    {
299        actualTC->setVecElem(reg, val);
300        checkerTC->setVecElem(reg, val);
301    }
302
303    void
304    setVecPredReg(const RegId& reg, const VecPredRegContainer& val)
305    {
306        actualTC->setVecPredReg(reg, val);
307        checkerTC->setVecPredReg(reg, val);
308    }
309
310    void
311    setCCReg(int reg_idx, CCReg val)
312    {
313        actualTC->setCCReg(reg_idx, val);
314        checkerTC->setCCReg(reg_idx, val);
315    }
316
317    /** Reads this thread's PC state. */
318    TheISA::PCState pcState()
319    { return actualTC->pcState(); }
320
321    /** Sets this thread's PC state. */
322    void
323    pcState(const TheISA::PCState &val)
324    {
325        DPRINTF(Checker, "Changing PC to %s, old PC %s\n",
326                         val, checkerTC->pcState());
327        checkerTC->pcState(val);
328        checkerCPU->recordPCChange(val);
329        return actualTC->pcState(val);
330    }
331
332    void
333    setNPC(Addr val)
334    {
335        checkerTC->setNPC(val);
336        actualTC->setNPC(val);
337    }
338
339    void
340    pcStateNoRecord(const TheISA::PCState &val)
341    {
342        return actualTC->pcState(val);
343    }
344
345    /** Reads this thread's PC. */
346    Addr instAddr()
347    { return actualTC->instAddr(); }
348
349    /** Reads this thread's next PC. */
350    Addr nextInstAddr()
351    { return actualTC->nextInstAddr(); }
352
353    /** Reads this thread's next PC. */
354    MicroPC microPC()
355    { return actualTC->microPC(); }
356
357    RegVal readMiscRegNoEffect(int misc_reg) const
358    { return actualTC->readMiscRegNoEffect(misc_reg); }
359
360    RegVal readMiscReg(int misc_reg)
361    { return actualTC->readMiscReg(misc_reg); }
362
363    void
364    setMiscRegNoEffect(int misc_reg, RegVal val)
365    {
366        DPRINTF(Checker, "Setting misc reg with no effect: %d to both Checker"
367                         " and O3..\n", misc_reg);
368        checkerTC->setMiscRegNoEffect(misc_reg, val);
369        actualTC->setMiscRegNoEffect(misc_reg, val);
370    }
371
372    void
373    setMiscReg(int misc_reg, RegVal val)
374    {
375        DPRINTF(Checker, "Setting misc reg with effect: %d to both Checker"
376                         " and O3..\n", misc_reg);
377        checkerTC->setMiscReg(misc_reg, val);
378        actualTC->setMiscReg(misc_reg, val);
379    }
380
381    RegId
382    flattenRegId(const RegId& regId) const
383    {
384        return actualTC->flattenRegId(regId);
385    }
386
387    unsigned readStCondFailures()
388    { return actualTC->readStCondFailures(); }
389
390    void
391    setStCondFailures(unsigned sc_failures)
392    {
393        actualTC->setStCondFailures(sc_failures);
394    }
395
396    Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
397
398    RegVal readIntRegFlat(int idx) { return actualTC->readIntRegFlat(idx); }
399
400    void
401    setIntRegFlat(int idx, RegVal val)
402    {
403        actualTC->setIntRegFlat(idx, val);
404    }
405
406    RegVal
407    readFloatRegFlat(int idx)
408    {
409        return actualTC->readFloatRegFlat(idx);
410    }
411
412    void
413    setFloatRegFlat(int idx, RegVal val)
414    {
415        actualTC->setFloatRegFlat(idx, val);
416    }
417
418    const VecRegContainer &
419    readVecRegFlat(int idx) const
420    {
421        return actualTC->readVecRegFlat(idx);
422    }
423
424    /**
425     * Read vector register for modification, flat indexing.
426     */
427    VecRegContainer &
428    getWritableVecRegFlat(int idx)
429    {
430        return actualTC->getWritableVecRegFlat(idx);
431    }
432
433    void setVecRegFlat(int idx, const VecRegContainer& val)
434    { actualTC->setVecRegFlat(idx, val); }
435
436    const VecElem& readVecElemFlat(const RegIndex& idx,
437                                   const ElemIndex& elem_idx) const
438    { return actualTC->readVecElemFlat(idx, elem_idx); }
439
440    void setVecElemFlat(const RegIndex& idx,
441                        const ElemIndex& elem_idx, const VecElem& val)
442    { actualTC->setVecElemFlat(idx, elem_idx, val); }
443
444    const VecPredRegContainer& readVecPredRegFlat(int idx) const override
445    { return actualTC->readVecPredRegFlat(idx); }
446
447    VecPredRegContainer& getWritableVecPredRegFlat(int idx) override
448    { return actualTC->getWritableVecPredRegFlat(idx); }
449
450    void setVecPredRegFlat(int idx, const VecPredRegContainer& val) override
451    { actualTC->setVecPredRegFlat(idx, val); }
452
453    CCReg readCCRegFlat(int idx)
454    { return actualTC->readCCRegFlat(idx); }
455
456    void setCCRegFlat(int idx, CCReg val)
457    { actualTC->setCCRegFlat(idx, val); }
458};
459
460#endif // __CPU_CHECKER_EXEC_CONTEXT_HH__
461