thread_context.hh revision 13557
18713Sandreas.hansson@arm.com/* 27090SN/A * Copyright (c) 2011-2012, 2016 ARM Limited 37090SN/A * Copyright (c) 2013 Advanced Micro Devices, Inc. 47090SN/A * All rights reserved 57090SN/A * 67090SN/A * The license below extends only to copyright in the software and shall 77090SN/A * not be construed as granting a license to any other intellectual 87090SN/A * property including but not limited to intellectual property relating 97090SN/A * to a hardware implementation of the functionality of the software 107090SN/A * licensed hereunder. You may use the software subject to the license 117090SN/A * terms below provided that you ensure that this notice is replicated 127090SN/A * unmodified and in its entirety in all distributions of the software, 134486SN/A * modified or unmodified, in source code or in binary form. 144486SN/A * 154486SN/A * Copyright (c) 2006 The Regents of The University of Michigan 164486SN/A * All rights reserved. 174486SN/A * 184486SN/A * Redistribution and use in source and binary forms, with or without 194486SN/A * modification, are permitted provided that the following conditions are 204486SN/A * met: redistributions of source code must retain the above copyright 214486SN/A * notice, this list of conditions and the following disclaimer; 224486SN/A * redistributions in binary form must reproduce the above copyright 234486SN/A * notice, this list of conditions and the following disclaimer in the 244486SN/A * documentation and/or other materials provided with the distribution; 254486SN/A * neither the name of the copyright holders nor the names of its 264486SN/A * contributors may be used to endorse or promote products derived from 274486SN/A * this software without specific prior written permission. 284486SN/A * 294486SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 304486SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 314486SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 324486SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 334486SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 344486SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 354486SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 364486SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 374486SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 384486SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 397584SAli.Saidi@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 407584SAli.Saidi@arm.com * 417754SWilliam.Wang@arm.com * Authors: Kevin Lim 424486SN/A */ 433630SN/A 443630SN/A#ifndef __CPU_CHECKER_THREAD_CONTEXT_HH__ 457587SAli.Saidi@arm.com#define __CPU_CHECKER_THREAD_CONTEXT_HH__ 468525SAli.Saidi@ARM.com 478525SAli.Saidi@ARM.com#include "arch/types.hh" 488212SAli.Saidi@ARM.com#include "config/the_isa.hh" 495478SN/A#include "cpu/checker/cpu.hh" 505478SN/A#include "cpu/simple_thread.hh" 517584SAli.Saidi@arm.com#include "cpu/thread_context.hh" 523630SN/A#include "debug/Checker.hh" 537584SAli.Saidi@arm.com 547584SAli.Saidi@arm.comclass EndQuiesceEvent; 557584SAli.Saidi@arm.comnamespace TheISA { 567584SAli.Saidi@arm.com namespace Kernel { 573898SN/A class Statistics; 587950SAli.Saidi@ARM.com }; 597950SAli.Saidi@ARM.com class Decoder; 607950SAli.Saidi@ARM.com}; 617950SAli.Saidi@ARM.com 627950SAli.Saidi@ARM.com/** 637950SAli.Saidi@ARM.com * Derived ThreadContext class for use with the Checker. The template 647950SAli.Saidi@ARM.com * parameter is the ThreadContext class used by the specific CPU being 657950SAli.Saidi@ARM.com * verified. This CheckerThreadContext is then used by the main CPU 667587SAli.Saidi@arm.com * in place of its usual ThreadContext class. It handles updating the 677587SAli.Saidi@arm.com * checker's state any time state is updated externally through the 687587SAli.Saidi@arm.com * ThreadContext. 697753SWilliam.Wang@arm.com */ 707753SWilliam.Wang@arm.comtemplate <class TC> 717753SWilliam.Wang@arm.comclass CheckerThreadContext : public ThreadContext 727753SWilliam.Wang@arm.com{ 737587SAli.Saidi@arm.com public: 747587SAli.Saidi@arm.com CheckerThreadContext(TC *actual_tc, 758282SAli.Saidi@ARM.com CheckerCPU *checker_cpu) 768282SAli.Saidi@ARM.com : actualTC(actual_tc), checkerTC(checker_cpu->thread), 778282SAli.Saidi@ARM.com checkerCPU(checker_cpu) 787584SAli.Saidi@arm.com { } 797584SAli.Saidi@arm.com 808524SAli.Saidi@ARM.com private: 818524SAli.Saidi@ARM.com /** The main CPU's ThreadContext, or class that implements the 828299Schander.sudanthi@arm.com * ThreadContext interface. */ 837584SAli.Saidi@arm.com TC *actualTC; 847584SAli.Saidi@arm.com /** The checker's own SimpleThread. Will be updated any time 857584SAli.Saidi@arm.com * anything uses this ThreadContext to externally update a 868742Sgblack@eecs.umich.edu * thread's state. */ 877584SAli.Saidi@arm.com SimpleThread *checkerTC; 887584SAli.Saidi@arm.com /** Pointer to the checker CPU. */ 897584SAli.Saidi@arm.com CheckerCPU *checkerCPU; 908283SPrakash.Ramrakhyani@arm.com 918283SPrakash.Ramrakhyani@arm.com public: 927584SAli.Saidi@arm.com 937584SAli.Saidi@arm.com BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); } 947584SAli.Saidi@arm.com 957584SAli.Saidi@arm.com uint32_t socketId() const { return actualTC->socketId(); } 967584SAli.Saidi@arm.com 977584SAli.Saidi@arm.com int cpuId() const { return actualTC->cpuId(); } 987584SAli.Saidi@arm.com 997584SAli.Saidi@arm.com ContextID contextId() const { return actualTC->contextId(); } 1007584SAli.Saidi@arm.com 1017584SAli.Saidi@arm.com void setContextId(ContextID id) 1027584SAli.Saidi@arm.com { 1037584SAli.Saidi@arm.com actualTC->setContextId(id); 1047584SAli.Saidi@arm.com checkerTC->setContextId(id); 1057584SAli.Saidi@arm.com } 1067584SAli.Saidi@arm.com 1077584SAli.Saidi@arm.com /** Returns this thread's ID number. */ 1087584SAli.Saidi@arm.com int threadId() const { return actualTC->threadId(); } 1097584SAli.Saidi@arm.com void setThreadId(int id) 1107584SAli.Saidi@arm.com { 1117584SAli.Saidi@arm.com checkerTC->setThreadId(id); 1127584SAli.Saidi@arm.com actualTC->setThreadId(id); 1137584SAli.Saidi@arm.com } 1147584SAli.Saidi@arm.com 1158512Sgeoffrey.blake@arm.com BaseTLB *getITBPtr() { return actualTC->getITBPtr(); } 1168512Sgeoffrey.blake@arm.com 1178512Sgeoffrey.blake@arm.com BaseTLB *getDTBPtr() { return actualTC->getDTBPtr(); } 1188512Sgeoffrey.blake@arm.com 1198512Sgeoffrey.blake@arm.com CheckerCPU *getCheckerCpuPtr() 1208512Sgeoffrey.blake@arm.com { 1218512Sgeoffrey.blake@arm.com return checkerCPU; 1227950SAli.Saidi@ARM.com } 1237754SWilliam.Wang@arm.com 1247950SAli.Saidi@ARM.com TheISA::Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); } 1257950SAli.Saidi@ARM.com 1267950SAli.Saidi@ARM.com System *getSystemPtr() { return actualTC->getSystemPtr(); } 1277754SWilliam.Wang@arm.com 1287754SWilliam.Wang@arm.com TheISA::Kernel::Statistics *getKernelStats() 1297753SWilliam.Wang@arm.com { return actualTC->getKernelStats(); } 1307753SWilliam.Wang@arm.com 1317753SWilliam.Wang@arm.com Process *getProcessPtr() { return actualTC->getProcessPtr(); } 1327950SAli.Saidi@ARM.com 1337753SWilliam.Wang@arm.com void setProcessPtr(Process *p) { actualTC->setProcessPtr(p); } 1347753SWilliam.Wang@arm.com 1357584SAli.Saidi@arm.com PortProxy &getPhysProxy() { return actualTC->getPhysProxy(); } 1367584SAli.Saidi@arm.com 1373630SN/A FSTranslatingPortProxy &getVirtProxy() 1388525SAli.Saidi@ARM.com { return actualTC->getVirtProxy(); } 1393630SN/A 1407753SWilliam.Wang@arm.com void initMemProxies(ThreadContext *tc) 1417753SWilliam.Wang@arm.com { actualTC->initMemProxies(tc); } 1427753SWilliam.Wang@arm.com 1437584SAli.Saidi@arm.com void connectMemPorts(ThreadContext *tc) 1447584SAli.Saidi@arm.com { 1457584SAli.Saidi@arm.com actualTC->connectMemPorts(tc); 1467584SAli.Saidi@arm.com } 1477584SAli.Saidi@arm.com 1487584SAli.Saidi@arm.com SETranslatingPortProxy &getMemProxy() { return actualTC->getMemProxy(); } 1498512Sgeoffrey.blake@arm.com 1507753SWilliam.Wang@arm.com /** Executes a syscall in SE mode. */ 1517754SWilliam.Wang@arm.com void syscall(int64_t callnum, Fault *fault) 1527950SAli.Saidi@ARM.com { return actualTC->syscall(callnum, fault); } 1538282SAli.Saidi@ARM.com 1548525SAli.Saidi@ARM.com Status status() const { return actualTC->status(); } 1558212SAli.Saidi@ARM.com 1568212SAli.Saidi@ARM.com void setStatus(Status new_status) 1578212SAli.Saidi@ARM.com { 1588212SAli.Saidi@ARM.com actualTC->setStatus(new_status); 1598212SAli.Saidi@ARM.com checkerTC->setStatus(new_status); 1607584SAli.Saidi@arm.com } 1617731SAli.Saidi@ARM.com 1628461SAli.Saidi@ARM.com /// Set the status to Active. 1638461SAli.Saidi@ARM.com void activate() { actualTC->activate(); } 1647696SAli.Saidi@ARM.com 1657696SAli.Saidi@ARM.com /// Set the status to Suspended. 1667696SAli.Saidi@ARM.com void suspend() { actualTC->suspend(); } 1677696SAli.Saidi@ARM.com 1687696SAli.Saidi@ARM.com /// Set the status to Halted. 1697696SAli.Saidi@ARM.com void halt() { actualTC->halt(); } 1707696SAli.Saidi@ARM.com 1717696SAli.Saidi@ARM.com void dumpFuncProfile() { actualTC->dumpFuncProfile(); } 1727696SAli.Saidi@ARM.com 1737696SAli.Saidi@ARM.com void takeOverFrom(ThreadContext *oldContext) 1747696SAli.Saidi@ARM.com { 1757696SAli.Saidi@ARM.com actualTC->takeOverFrom(oldContext); 1767696SAli.Saidi@ARM.com checkerTC->copyState(oldContext); 1777696SAli.Saidi@ARM.com } 1787696SAli.Saidi@ARM.com 1797696SAli.Saidi@ARM.com void regStats(const std::string &name) 1807696SAli.Saidi@ARM.com { 1818713Sandreas.hansson@arm.com actualTC->regStats(name); 1828713Sandreas.hansson@arm.com checkerTC->regStats(name); 1838713Sandreas.hansson@arm.com } 1847696SAli.Saidi@ARM.com 1857696SAli.Saidi@ARM.com EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); } 1868282SAli.Saidi@ARM.com 1878512Sgeoffrey.blake@arm.com Tick readLastActivate() { return actualTC->readLastActivate(); } 1888713Sandreas.hansson@arm.com Tick readLastSuspend() { return actualTC->readLastSuspend(); } 1898713Sandreas.hansson@arm.com 1908713Sandreas.hansson@arm.com void profileClear() { return actualTC->profileClear(); } 1918713Sandreas.hansson@arm.com void profileSample() { return actualTC->profileSample(); } 1928713Sandreas.hansson@arm.com 1937696SAli.Saidi@ARM.com // @todo: Do I need this? 1947696SAli.Saidi@ARM.com void copyArchRegs(ThreadContext *tc) 1957696SAli.Saidi@ARM.com { 1967696SAli.Saidi@ARM.com actualTC->copyArchRegs(tc); 1977696SAli.Saidi@ARM.com checkerTC->copyArchRegs(tc); 1987696SAli.Saidi@ARM.com } 1997696SAli.Saidi@ARM.com 2007696SAli.Saidi@ARM.com void clearArchRegs() 2017696SAli.Saidi@ARM.com { 2027753SWilliam.Wang@arm.com actualTC->clearArchRegs(); 2038714Sandreas.hansson@arm.com checkerTC->clearArchRegs(); 2047754SWilliam.Wang@arm.com } 2057754SWilliam.Wang@arm.com 2068212SAli.Saidi@ARM.com // 2078714Sandreas.hansson@arm.com // New accessors for new decoder. 2088714Sandreas.hansson@arm.com // 2097696SAli.Saidi@ARM.com RegVal readIntReg(int reg_idx) { return actualTC->readIntReg(reg_idx); } 2107696SAli.Saidi@ARM.com 2117696SAli.Saidi@ARM.com RegVal 2127696SAli.Saidi@ARM.com readFloatRegBits(int reg_idx) 2137696SAli.Saidi@ARM.com { 2147696SAli.Saidi@ARM.com return actualTC->readFloatRegBits(reg_idx); 2157696SAli.Saidi@ARM.com } 2167696SAli.Saidi@ARM.com 2177696SAli.Saidi@ARM.com const VecRegContainer& readVecReg(const RegId& reg) const 2187696SAli.Saidi@ARM.com { return actualTC->readVecReg(reg); } 2197696SAli.Saidi@ARM.com 2207696SAli.Saidi@ARM.com /** 2217696SAli.Saidi@ARM.com * Read vector register for modification, hierarchical indexing. 2227696SAli.Saidi@ARM.com */ 2237696SAli.Saidi@ARM.com VecRegContainer& getWritableVecReg(const RegId& reg) 2247696SAli.Saidi@ARM.com { return actualTC->getWritableVecReg(reg); } 2257696SAli.Saidi@ARM.com 2267754SWilliam.Wang@arm.com /** Vector Register Lane Interfaces. */ 2277754SWilliam.Wang@arm.com /** @{ */ 2287754SWilliam.Wang@arm.com /** Reads source vector 8bit operand. */ 2297696SAli.Saidi@ARM.com ConstVecLane8 2307696SAli.Saidi@ARM.com readVec8BitLaneReg(const RegId& reg) const 2317696SAli.Saidi@ARM.com { return actualTC->readVec8BitLaneReg(reg); } 2327696SAli.Saidi@ARM.com 2337696SAli.Saidi@ARM.com /** Reads source vector 16bit operand. */ 2347696SAli.Saidi@ARM.com ConstVecLane16 2357754SWilliam.Wang@arm.com readVec16BitLaneReg(const RegId& reg) const 2367754SWilliam.Wang@arm.com { return actualTC->readVec16BitLaneReg(reg); } 2377950SAli.Saidi@ARM.com 2387696SAli.Saidi@ARM.com /** Reads source vector 32bit operand. */ 2397696SAli.Saidi@ARM.com ConstVecLane32 2408461SAli.Saidi@ARM.com readVec32BitLaneReg(const RegId& reg) const 2418461SAli.Saidi@ARM.com { return actualTC->readVec32BitLaneReg(reg); } 2427584SAli.Saidi@arm.com 2437584SAli.Saidi@arm.com /** Reads source vector 64bit operand. */ 2447584SAli.Saidi@arm.com ConstVecLane64 2457584SAli.Saidi@arm.com readVec64BitLaneReg(const RegId& reg) const 2468299Schander.sudanthi@arm.com { return actualTC->readVec64BitLaneReg(reg); } 2477584SAli.Saidi@arm.com 2487584SAli.Saidi@arm.com /** Write a lane of the destination vector register. */ 2497584SAli.Saidi@arm.com virtual void setVecLane(const RegId& reg, 2507584SAli.Saidi@arm.com const LaneData<LaneSize::Byte>& val) 2517584SAli.Saidi@arm.com { return actualTC->setVecLane(reg, val); } 2527584SAli.Saidi@arm.com virtual void setVecLane(const RegId& reg, 2537584SAli.Saidi@arm.com const LaneData<LaneSize::TwoByte>& val) 2547584SAli.Saidi@arm.com { return actualTC->setVecLane(reg, val); } 2557584SAli.Saidi@arm.com virtual void setVecLane(const RegId& reg, 2567584SAli.Saidi@arm.com const LaneData<LaneSize::FourByte>& val) 2577584SAli.Saidi@arm.com { return actualTC->setVecLane(reg, val); } 2587584SAli.Saidi@arm.com virtual void setVecLane(const RegId& reg, 2597584SAli.Saidi@arm.com const LaneData<LaneSize::EightByte>& val) 2607584SAli.Saidi@arm.com { return actualTC->setVecLane(reg, val); } 2618713Sandreas.hansson@arm.com /** @} */ 2628713Sandreas.hansson@arm.com 2638713Sandreas.hansson@arm.com const VecElem& readVecElem(const RegId& reg) const 2647584SAli.Saidi@arm.com { return actualTC->readVecElem(reg); } 2657584SAli.Saidi@arm.com 2668713Sandreas.hansson@arm.com CCReg readCCReg(int reg_idx) 2678713Sandreas.hansson@arm.com { return actualTC->readCCReg(reg_idx); } 2688713Sandreas.hansson@arm.com 2698713Sandreas.hansson@arm.com void 2708713Sandreas.hansson@arm.com setIntReg(int reg_idx, RegVal val) 2714104SN/A { 2723630SN/A actualTC->setIntReg(reg_idx, val); 2733630SN/A checkerTC->setIntReg(reg_idx, val); 2743630SN/A } 2753630SN/A 2767584SAli.Saidi@arm.com void 2777584SAli.Saidi@arm.com setFloatRegBits(int reg_idx, RegVal val) 2787584SAli.Saidi@arm.com { 2797584SAli.Saidi@arm.com actualTC->setFloatRegBits(reg_idx, val); 2807753SWilliam.Wang@arm.com checkerTC->setFloatRegBits(reg_idx, val); 2818714Sandreas.hansson@arm.com } 2827754SWilliam.Wang@arm.com 2837754SWilliam.Wang@arm.com void 2847584SAli.Saidi@arm.com setVecReg(const RegId& reg, const VecRegContainer& val) 2857584SAli.Saidi@arm.com { 2867584SAli.Saidi@arm.com actualTC->setVecReg(reg, val); 2877584SAli.Saidi@arm.com checkerTC->setVecReg(reg, val); 2887584SAli.Saidi@arm.com } 2897584SAli.Saidi@arm.com 2907584SAli.Saidi@arm.com void 2917584SAli.Saidi@arm.com setVecElem(const RegId& reg, const VecElem& val) 2927584SAli.Saidi@arm.com { 2937584SAli.Saidi@arm.com actualTC->setVecElem(reg, val); 2947584SAli.Saidi@arm.com checkerTC->setVecElem(reg, val); 2957584SAli.Saidi@arm.com } 2967584SAli.Saidi@arm.com 2977584SAli.Saidi@arm.com void 2987584SAli.Saidi@arm.com setCCReg(int reg_idx, CCReg val) 2998299Schander.sudanthi@arm.com { 3008299Schander.sudanthi@arm.com actualTC->setCCReg(reg_idx, val); 3017584SAli.Saidi@arm.com checkerTC->setCCReg(reg_idx, val); 3028525SAli.Saidi@ARM.com } 3038525SAli.Saidi@ARM.com 3048524SAli.Saidi@ARM.com /** Reads this thread's PC state. */ 3058524SAli.Saidi@ARM.com TheISA::PCState pcState() 3068524SAli.Saidi@ARM.com { return actualTC->pcState(); } 3078524SAli.Saidi@ARM.com 3088524SAli.Saidi@ARM.com /** Sets this thread's PC state. */ 3098524SAli.Saidi@ARM.com void 3108524SAli.Saidi@ARM.com pcState(const TheISA::PCState &val) 3118524SAli.Saidi@ARM.com { 3128524SAli.Saidi@ARM.com DPRINTF(Checker, "Changing PC to %s, old PC %s\n", 3138524SAli.Saidi@ARM.com val, checkerTC->pcState()); 3148524SAli.Saidi@ARM.com checkerTC->pcState(val); 3158524SAli.Saidi@ARM.com checkerCPU->recordPCChange(val); 3168524SAli.Saidi@ARM.com return actualTC->pcState(val); 3178524SAli.Saidi@ARM.com } 3188524SAli.Saidi@ARM.com 3198525SAli.Saidi@ARM.com void 3208524SAli.Saidi@ARM.com setNPC(Addr val) 3218524SAli.Saidi@ARM.com { 3228524SAli.Saidi@ARM.com checkerTC->setNPC(val); 3238524SAli.Saidi@ARM.com actualTC->setNPC(val); 3248524SAli.Saidi@ARM.com } 3258525SAli.Saidi@ARM.com 3268525SAli.Saidi@ARM.com void 3278525SAli.Saidi@ARM.com pcStateNoRecord(const TheISA::PCState &val) 3288525SAli.Saidi@ARM.com { 3298525SAli.Saidi@ARM.com return actualTC->pcState(val); 3308525SAli.Saidi@ARM.com } 3318525SAli.Saidi@ARM.com 3328524SAli.Saidi@ARM.com /** Reads this thread's PC. */ 3338524SAli.Saidi@ARM.com Addr instAddr() 3348524SAli.Saidi@ARM.com { return actualTC->instAddr(); } 3358524SAli.Saidi@ARM.com 3368524SAli.Saidi@ARM.com /** Reads this thread's next PC. */ 3378524SAli.Saidi@ARM.com Addr nextInstAddr() 3388524SAli.Saidi@ARM.com { return actualTC->nextInstAddr(); } 3398524SAli.Saidi@ARM.com 3408524SAli.Saidi@ARM.com /** Reads this thread's next PC. */ 3418524SAli.Saidi@ARM.com MicroPC microPC() 3428524SAli.Saidi@ARM.com { return actualTC->microPC(); } 3438524SAli.Saidi@ARM.com 3448524SAli.Saidi@ARM.com RegVal readMiscRegNoEffect(int misc_reg) const 3458524SAli.Saidi@ARM.com { return actualTC->readMiscRegNoEffect(misc_reg); } 3468524SAli.Saidi@ARM.com 3478524SAli.Saidi@ARM.com RegVal readMiscReg(int misc_reg) 3488524SAli.Saidi@ARM.com { return actualTC->readMiscReg(misc_reg); } 3498713Sandreas.hansson@arm.com 3508713Sandreas.hansson@arm.com void 3518713Sandreas.hansson@arm.com setMiscRegNoEffect(int misc_reg, const RegVal &val) 3528524SAli.Saidi@ARM.com { 3538524SAli.Saidi@ARM.com DPRINTF(Checker, "Setting misc reg with no effect: %d to both Checker" 3548810SAli.Saidi@ARM.com " and O3..\n", misc_reg); 3558713Sandreas.hansson@arm.com checkerTC->setMiscRegNoEffect(misc_reg, val); 3568713Sandreas.hansson@arm.com actualTC->setMiscRegNoEffect(misc_reg, val); 3578713Sandreas.hansson@arm.com } 3588810SAli.Saidi@ARM.com 3598524SAli.Saidi@ARM.com void 3608524SAli.Saidi@ARM.com setMiscReg(int misc_reg, const RegVal &val) 3618524SAli.Saidi@ARM.com { 3628524SAli.Saidi@ARM.com DPRINTF(Checker, "Setting misc reg with effect: %d to both Checker" 3638524SAli.Saidi@ARM.com " and O3..\n", misc_reg); 3648524SAli.Saidi@ARM.com checkerTC->setMiscReg(misc_reg, val); 3658524SAli.Saidi@ARM.com actualTC->setMiscReg(misc_reg, val); 3668524SAli.Saidi@ARM.com } 3678524SAli.Saidi@ARM.com 3688524SAli.Saidi@ARM.com RegId 3698524SAli.Saidi@ARM.com flattenRegId(const RegId& regId) const 3708524SAli.Saidi@ARM.com { 3718524SAli.Saidi@ARM.com return actualTC->flattenRegId(regId); 3728714Sandreas.hansson@arm.com } 3738524SAli.Saidi@ARM.com 3748524SAli.Saidi@ARM.com unsigned readStCondFailures() 3758524SAli.Saidi@ARM.com { return actualTC->readStCondFailures(); } 3768524SAli.Saidi@ARM.com 3778524SAli.Saidi@ARM.com void 3788714Sandreas.hansson@arm.com setStCondFailures(unsigned sc_failures) 3798714Sandreas.hansson@arm.com { 3808525SAli.Saidi@ARM.com actualTC->setStCondFailures(sc_failures); 3818714Sandreas.hansson@arm.com } 3828714Sandreas.hansson@arm.com 3838525SAli.Saidi@ARM.com Counter readFuncExeInst() { return actualTC->readFuncExeInst(); } 3848714Sandreas.hansson@arm.com 3858714Sandreas.hansson@arm.com RegVal readIntRegFlat(int idx) { return actualTC->readIntRegFlat(idx); } 3868525SAli.Saidi@ARM.com 3878525SAli.Saidi@ARM.com void 3888525SAli.Saidi@ARM.com setIntRegFlat(int idx, RegVal val) 3898524SAli.Saidi@ARM.com { 3908524SAli.Saidi@ARM.com actualTC->setIntRegFlat(idx, val); 3918524SAli.Saidi@ARM.com } 3928524SAli.Saidi@ARM.com 3938524SAli.Saidi@ARM.com RegVal 3948524SAli.Saidi@ARM.com readFloatRegBitsFlat(int idx) 3958524SAli.Saidi@ARM.com { 3968524SAli.Saidi@ARM.com return actualTC->readFloatRegBitsFlat(idx); 3978524SAli.Saidi@ARM.com } 3988524SAli.Saidi@ARM.com 3998524SAli.Saidi@ARM.com void 4008524SAli.Saidi@ARM.com setFloatRegBitsFlat(int idx, RegVal val) 4018524SAli.Saidi@ARM.com { 4028524SAli.Saidi@ARM.com actualTC->setFloatRegBitsFlat(idx, val); 4038524SAli.Saidi@ARM.com } 4048524SAli.Saidi@ARM.com 405 const VecRegContainer & 406 readVecRegFlat(int idx) const 407 { 408 return actualTC->readVecRegFlat(idx); 409 } 410 411 /** 412 * Read vector register for modification, flat indexing. 413 */ 414 VecRegContainer & 415 getWritableVecRegFlat(int idx) 416 { 417 return actualTC->getWritableVecRegFlat(idx); 418 } 419 420 void setVecRegFlat(int idx, const VecRegContainer& val) 421 { actualTC->setVecRegFlat(idx, val); } 422 423 const VecElem& readVecElemFlat(const RegIndex& idx, 424 const ElemIndex& elem_idx) const 425 { return actualTC->readVecElemFlat(idx, elem_idx); } 426 427 void setVecElemFlat(const RegIndex& idx, 428 const ElemIndex& elem_idx, const VecElem& val) 429 { actualTC->setVecElemFlat(idx, elem_idx, val); } 430 431 CCReg readCCRegFlat(int idx) 432 { return actualTC->readCCRegFlat(idx); } 433 434 void setCCRegFlat(int idx, CCReg val) 435 { actualTC->setCCRegFlat(idx, val); } 436}; 437 438#endif // __CPU_CHECKER_EXEC_CONTEXT_HH__ 439