thread_context.hh revision 10934:5af8f40d8f2c 
1/*
2 * Copyright (c) 2011-2012 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder.  You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 */
43
44#ifndef __CPU_CHECKER_THREAD_CONTEXT_HH__
45#define __CPU_CHECKER_THREAD_CONTEXT_HH__
46
47#include "arch/types.hh"
48#include "config/the_isa.hh"
49#include "cpu/checker/cpu.hh"
50#include "cpu/simple_thread.hh"
51#include "cpu/thread_context.hh"
52#include "debug/Checker.hh"
53
54class EndQuiesceEvent;
55namespace TheISA {
56    namespace Kernel {
57        class Statistics;
58    };
59    class Decoder;
60};
61
62/**
63 * Derived ThreadContext class for use with the Checker.  The template
64 * parameter is the ThreadContext class used by the specific CPU being
65 * verified.  This CheckerThreadContext is then used by the main CPU
66 * in place of its usual ThreadContext class.  It handles updating the
67 * checker's state any time state is updated externally through the
68 * ThreadContext.
69 */
70template <class TC>
71class CheckerThreadContext : public ThreadContext
72{
73  public:
74    CheckerThreadContext(TC *actual_tc,
75                         CheckerCPU *checker_cpu)
76        : actualTC(actual_tc), checkerTC(checker_cpu->thread),
77          checkerCPU(checker_cpu)
78    { }
79
80  private:
81    /** The main CPU's ThreadContext, or class that implements the
82     * ThreadContext interface. */
83    TC *actualTC;
84    /** The checker's own SimpleThread. Will be updated any time
85     * anything uses this ThreadContext to externally update a
86     * thread's state. */
87    SimpleThread *checkerTC;
88    /** Pointer to the checker CPU. */
89    CheckerCPU *checkerCPU;
90
91  public:
92
93    BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); }
94
95    uint32_t socketId() const { return actualTC->socketId(); }
96
97    int cpuId() const { return actualTC->cpuId(); }
98
99    int contextId() const { return actualTC->contextId(); }
100
101    void setContextId(int id)
102    {
103       actualTC->setContextId(id);
104       checkerTC->setContextId(id);
105    }
106
107    /** Returns this thread's ID number. */
108    int threadId() const { return actualTC->threadId(); }
109    void setThreadId(int id)
110    {
111        checkerTC->setThreadId(id);
112        actualTC->setThreadId(id);
113    }
114
115    TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); }
116
117    TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); }
118
119    CheckerCPU *getCheckerCpuPtr()
120    {
121        return checkerCPU;
122    }
123
124    TheISA::Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); }
125
126    System *getSystemPtr() { return actualTC->getSystemPtr(); }
127
128    TheISA::Kernel::Statistics *getKernelStats()
129    { return actualTC->getKernelStats(); }
130
131    Process *getProcessPtr() { return actualTC->getProcessPtr(); }
132
133    PortProxy &getPhysProxy() { return actualTC->getPhysProxy(); }
134
135    FSTranslatingPortProxy &getVirtProxy()
136    { return actualTC->getVirtProxy(); }
137
138    void initMemProxies(ThreadContext *tc)
139    { actualTC->initMemProxies(tc); }
140
141    void connectMemPorts(ThreadContext *tc)
142    {
143        actualTC->connectMemPorts(tc);
144    }
145
146    SETranslatingPortProxy &getMemProxy() { return actualTC->getMemProxy(); }
147
148    /** Executes a syscall in SE mode. */
149    void syscall(int64_t callnum)
150    { return actualTC->syscall(callnum); }
151
152    Status status() const { return actualTC->status(); }
153
154    void setStatus(Status new_status)
155    {
156        actualTC->setStatus(new_status);
157        checkerTC->setStatus(new_status);
158    }
159
160    /// Set the status to Active.
161    void activate() { actualTC->activate(); }
162
163    /// Set the status to Suspended.
164    void suspend() { actualTC->suspend(); }
165
166    /// Set the status to Halted.
167    void halt() { actualTC->halt(); }
168
169    void dumpFuncProfile() { actualTC->dumpFuncProfile(); }
170
171    void takeOverFrom(ThreadContext *oldContext)
172    {
173        actualTC->takeOverFrom(oldContext);
174        checkerTC->copyState(oldContext);
175    }
176
177    void regStats(const std::string &name)
178    {
179        actualTC->regStats(name);
180        checkerTC->regStats(name);
181    }
182
183    EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); }
184
185    Tick readLastActivate() { return actualTC->readLastActivate(); }
186    Tick readLastSuspend() { return actualTC->readLastSuspend(); }
187
188    void profileClear() { return actualTC->profileClear(); }
189    void profileSample() { return actualTC->profileSample(); }
190
191    // @todo: Do I need this?
192    void copyArchRegs(ThreadContext *tc)
193    {
194        actualTC->copyArchRegs(tc);
195        checkerTC->copyArchRegs(tc);
196    }
197
198    void clearArchRegs()
199    {
200        actualTC->clearArchRegs();
201        checkerTC->clearArchRegs();
202    }
203
204    //
205    // New accessors for new decoder.
206    //
207    uint64_t readIntReg(int reg_idx)
208    { return actualTC->readIntReg(reg_idx); }
209
210    FloatReg readFloatReg(int reg_idx)
211    { return actualTC->readFloatReg(reg_idx); }
212
213    FloatRegBits readFloatRegBits(int reg_idx)
214    { return actualTC->readFloatRegBits(reg_idx); }
215
216    CCReg readCCReg(int reg_idx)
217    { return actualTC->readCCReg(reg_idx); }
218
219    const VectorReg &readVectorReg(int reg_idx)
220    { return actualTC->readVectorReg(reg_idx); }
221
222    void setIntReg(int reg_idx, uint64_t val)
223    {
224        actualTC->setIntReg(reg_idx, val);
225        checkerTC->setIntReg(reg_idx, val);
226    }
227
228    void setFloatReg(int reg_idx, FloatReg val)
229    {
230        actualTC->setFloatReg(reg_idx, val);
231        checkerTC->setFloatReg(reg_idx, val);
232    }
233
234    void setFloatRegBits(int reg_idx, FloatRegBits val)
235    {
236        actualTC->setFloatRegBits(reg_idx, val);
237        checkerTC->setFloatRegBits(reg_idx, val);
238    }
239
240    void setCCReg(int reg_idx, CCReg val)
241    {
242        actualTC->setCCReg(reg_idx, val);
243        checkerTC->setCCReg(reg_idx, val);
244    }
245
246    void setVectorReg(int reg_idx, const VectorReg &val)
247    {
248        actualTC->setVectorReg(reg_idx, val);
249        checkerTC->setVectorReg(reg_idx, val);
250    }
251
252    /** Reads this thread's PC state. */
253    TheISA::PCState pcState()
254    { return actualTC->pcState(); }
255
256    /** Sets this thread's PC state. */
257    void pcState(const TheISA::PCState &val)
258    {
259        DPRINTF(Checker, "Changing PC to %s, old PC %s\n",
260                         val, checkerTC->pcState());
261        checkerTC->pcState(val);
262        checkerCPU->recordPCChange(val);
263        return actualTC->pcState(val);
264    }
265
266    void pcStateNoRecord(const TheISA::PCState &val)
267    {
268        return actualTC->pcState(val);
269    }
270
271    /** Reads this thread's PC. */
272    Addr instAddr()
273    { return actualTC->instAddr(); }
274
275    /** Reads this thread's next PC. */
276    Addr nextInstAddr()
277    { return actualTC->nextInstAddr(); }
278
279    /** Reads this thread's next PC. */
280    MicroPC microPC()
281    { return actualTC->microPC(); }
282
283    MiscReg readMiscRegNoEffect(int misc_reg) const
284    { return actualTC->readMiscRegNoEffect(misc_reg); }
285
286    MiscReg readMiscReg(int misc_reg)
287    { return actualTC->readMiscReg(misc_reg); }
288
289    void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
290    {
291        DPRINTF(Checker, "Setting misc reg with no effect: %d to both Checker"
292                         " and O3..\n", misc_reg);
293        checkerTC->setMiscRegNoEffect(misc_reg, val);
294        actualTC->setMiscRegNoEffect(misc_reg, val);
295    }
296
297    void setMiscReg(int misc_reg, const MiscReg &val)
298    {
299        DPRINTF(Checker, "Setting misc reg with effect: %d to both Checker"
300                         " and O3..\n", misc_reg);
301        checkerTC->setMiscReg(misc_reg, val);
302        actualTC->setMiscReg(misc_reg, val);
303    }
304
305    int flattenIntIndex(int reg) { return actualTC->flattenIntIndex(reg); }
306    int flattenFloatIndex(int reg) { return actualTC->flattenFloatIndex(reg); }
307    int flattenCCIndex(int reg) { return actualTC->flattenCCIndex(reg); }
308    int flattenVectorIndex(int reg) { return actualTC->flattenVectorIndex(reg); }
309    int flattenMiscIndex(int reg) { return actualTC->flattenMiscIndex(reg); }
310
311    unsigned readStCondFailures()
312    { return actualTC->readStCondFailures(); }
313
314    void setStCondFailures(unsigned sc_failures)
315    {
316        actualTC->setStCondFailures(sc_failures);
317    }
318
319    Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
320
321    uint64_t readIntRegFlat(int idx)
322    { return actualTC->readIntRegFlat(idx); }
323
324    void setIntRegFlat(int idx, uint64_t val)
325    { actualTC->setIntRegFlat(idx, val); }
326
327    FloatReg readFloatRegFlat(int idx)
328    { return actualTC->readFloatRegFlat(idx); }
329
330    void setFloatRegFlat(int idx, FloatReg val)
331    { actualTC->setFloatRegFlat(idx, val); }
332
333    FloatRegBits readFloatRegBitsFlat(int idx)
334    { return actualTC->readFloatRegBitsFlat(idx); }
335
336    void setFloatRegBitsFlat(int idx, FloatRegBits val)
337    { actualTC->setFloatRegBitsFlat(idx, val); }
338
339    CCReg readCCRegFlat(int idx)
340    { return actualTC->readCCRegFlat(idx); }
341
342    void setCCRegFlat(int idx, CCReg val)
343    { actualTC->setCCRegFlat(idx, val); }
344
345    const VectorReg &readVectorRegFlat(int idx)
346    { return actualTC->readVectorRegFlat(idx); }
347
348    void setVectorRegFlat(int idx, const VectorReg &val)
349    { actualTC->setVectorRegFlat(idx, val); }
350};
351
352#endif // __CPU_CHECKER_EXEC_CONTEXT_HH__
353