thread_context.hh revision 8706
12330SN/A/* 22330SN/A * Copyright (c) 2006 The Regents of The University of Michigan 32330SN/A * All rights reserved. 42330SN/A * 52330SN/A * Redistribution and use in source and binary forms, with or without 62330SN/A * modification, are permitted provided that the following conditions are 72330SN/A * met: redistributions of source code must retain the above copyright 82330SN/A * notice, this list of conditions and the following disclaimer; 92330SN/A * redistributions in binary form must reproduce the above copyright 102330SN/A * notice, this list of conditions and the following disclaimer in the 112330SN/A * documentation and/or other materials provided with the distribution; 122330SN/A * neither the name of the copyright holders nor the names of its 132330SN/A * contributors may be used to endorse or promote products derived from 142330SN/A * this software without specific prior written permission. 152330SN/A * 162330SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172330SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182330SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192330SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202330SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212330SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222330SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232330SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242330SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252330SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262330SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272689Sktlim@umich.edu * 282689Sktlim@umich.edu * Authors: Kevin Lim 292330SN/A */ 302330SN/A 312683Sktlim@umich.edu#ifndef __CPU_CHECKER_THREAD_CONTEXT_HH__ 322683Sktlim@umich.edu#define __CPU_CHECKER_THREAD_CONTEXT_HH__ 332315SN/A 342972Sgblack@eecs.umich.edu#include "arch/types.hh" 356658Snate@binkert.org#include "config/the_isa.hh" 362315SN/A#include "cpu/checker/cpu.hh" 372683Sktlim@umich.edu#include "cpu/simple_thread.hh" 382680SN/A#include "cpu/thread_context.hh" 392315SN/A 402315SN/Aclass EndQuiesceEvent; 413548Sgblack@eecs.umich.edunamespace TheISA { 423548Sgblack@eecs.umich.edu namespace Kernel { 433548Sgblack@eecs.umich.edu class Statistics; 443548Sgblack@eecs.umich.edu }; 452330SN/A}; 462315SN/A 472350SN/A/** 482680SN/A * Derived ThreadContext class for use with the Checker. The template 492680SN/A * parameter is the ThreadContext class used by the specific CPU being 502683Sktlim@umich.edu * verified. This CheckerThreadContext is then used by the main CPU 512683Sktlim@umich.edu * in place of its usual ThreadContext class. It handles updating the 522683Sktlim@umich.edu * checker's state any time state is updated externally through the 532683Sktlim@umich.edu * ThreadContext. 542350SN/A */ 552680SN/Atemplate <class TC> 562680SN/Aclass CheckerThreadContext : public ThreadContext 572315SN/A{ 582315SN/A public: 592680SN/A CheckerThreadContext(TC *actual_tc, 602683Sktlim@umich.edu CheckerCPU *checker_cpu) 612683Sktlim@umich.edu : actualTC(actual_tc), checkerTC(checker_cpu->thread), 622330SN/A checkerCPU(checker_cpu) 632315SN/A { } 642315SN/A 652315SN/A private: 662683Sktlim@umich.edu /** The main CPU's ThreadContext, or class that implements the 672683Sktlim@umich.edu * ThreadContext interface. */ 682680SN/A TC *actualTC; 692683Sktlim@umich.edu /** The checker's own SimpleThread. Will be updated any time 702683Sktlim@umich.edu * anything uses this ThreadContext to externally update a 712683Sktlim@umich.edu * thread's state. */ 722683Sktlim@umich.edu SimpleThread *checkerTC; 732683Sktlim@umich.edu /** Pointer to the checker CPU. */ 742315SN/A CheckerCPU *checkerCPU; 752315SN/A 762315SN/A public: 772315SN/A 782680SN/A BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); } 792315SN/A 802315SN/A void setCpuId(int id) 812315SN/A { 822680SN/A actualTC->setCpuId(id); 832680SN/A checkerTC->setCpuId(id); 842315SN/A } 852315SN/A 865712Shsul@eecs.umich.edu int cpuId() { return actualTC->cpuId(); } 872315SN/A 886022Sgblack@eecs.umich.edu TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); } 894997Sgblack@eecs.umich.edu 906022Sgblack@eecs.umich.edu TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); } 914997Sgblack@eecs.umich.edu 922315SN/A#if FULL_SYSTEM 932680SN/A System *getSystemPtr() { return actualTC->getSystemPtr(); } 942315SN/A 952680SN/A PhysicalMemory *getPhysMemPtr() { return actualTC->getPhysMemPtr(); } 962315SN/A 973548Sgblack@eecs.umich.edu TheISA::Kernel::Statistics *getKernelStats() 983548Sgblack@eecs.umich.edu { return actualTC->getKernelStats(); } 992690Sktlim@umich.edu 1008706Sandreas.hansson@arm.com PortProxy* getPhysProxy() { return actualTC->getPhysProxy(); } 1012690Sktlim@umich.edu 1028706Sandreas.hansson@arm.com FSTranslatingPortProxy* getVirtProxy() 1038706Sandreas.hansson@arm.com { return actualTC->getVirtProxy(); } 1042315SN/A#else 1058706Sandreas.hansson@arm.com SETranslatingPortProxy* getMemProxy() { return actualTC->getMemProxy(); } 1062690Sktlim@umich.edu 1072680SN/A Process *getProcessPtr() { return actualTC->getProcessPtr(); } 1082315SN/A#endif 1092315SN/A 1102680SN/A Status status() const { return actualTC->status(); } 1112315SN/A 1122315SN/A void setStatus(Status new_status) 1132330SN/A { 1142680SN/A actualTC->setStatus(new_status); 1152680SN/A checkerTC->setStatus(new_status); 1162330SN/A } 1172315SN/A 1182315SN/A /// Set the status to Active. Optional delay indicates number of 1192315SN/A /// cycles to wait before beginning execution. 1202680SN/A void activate(int delay = 1) { actualTC->activate(delay); } 1212315SN/A 1222315SN/A /// Set the status to Suspended. 1232680SN/A void suspend() { actualTC->suspend(); } 1242315SN/A 1252315SN/A /// Set the status to Halted. 1262680SN/A void halt() { actualTC->halt(); } 1272315SN/A 1282315SN/A#if FULL_SYSTEM 1292680SN/A void dumpFuncProfile() { actualTC->dumpFuncProfile(); } 1302315SN/A#endif 1312315SN/A 1322680SN/A void takeOverFrom(ThreadContext *oldContext) 1332315SN/A { 1342680SN/A actualTC->takeOverFrom(oldContext); 1353225Sktlim@umich.edu checkerTC->copyState(oldContext); 1362315SN/A } 1372315SN/A 1382680SN/A void regStats(const std::string &name) { actualTC->regStats(name); } 1392315SN/A 1402680SN/A void serialize(std::ostream &os) { actualTC->serialize(os); } 1412315SN/A void unserialize(Checkpoint *cp, const std::string §ion) 1422680SN/A { actualTC->unserialize(cp, section); } 1432315SN/A 1442315SN/A#if FULL_SYSTEM 1452680SN/A EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); } 1462315SN/A 1472680SN/A Tick readLastActivate() { return actualTC->readLastActivate(); } 1482680SN/A Tick readLastSuspend() { return actualTC->readLastSuspend(); } 1492315SN/A 1502680SN/A void profileClear() { return actualTC->profileClear(); } 1512680SN/A void profileSample() { return actualTC->profileSample(); } 1522315SN/A#endif 1532315SN/A 1545715Shsul@eecs.umich.edu int threadId() { return actualTC->threadId(); } 1552315SN/A 1562315SN/A // @todo: Do I need this? 1572680SN/A void copyArchRegs(ThreadContext *tc) 1582315SN/A { 1592680SN/A actualTC->copyArchRegs(tc); 1602680SN/A checkerTC->copyArchRegs(tc); 1612315SN/A } 1622315SN/A 1632315SN/A void clearArchRegs() 1642315SN/A { 1652680SN/A actualTC->clearArchRegs(); 1662680SN/A checkerTC->clearArchRegs(); 1672315SN/A } 1682315SN/A 1692315SN/A // 1702315SN/A // New accessors for new decoder. 1712315SN/A // 1722315SN/A uint64_t readIntReg(int reg_idx) 1732680SN/A { return actualTC->readIntReg(reg_idx); } 1742315SN/A 1752669SN/A FloatReg readFloatReg(int reg_idx) 1762680SN/A { return actualTC->readFloatReg(reg_idx); } 1772315SN/A 1782669SN/A FloatRegBits readFloatRegBits(int reg_idx) 1792680SN/A { return actualTC->readFloatRegBits(reg_idx); } 1802315SN/A 1812315SN/A void setIntReg(int reg_idx, uint64_t val) 1822315SN/A { 1832680SN/A actualTC->setIntReg(reg_idx, val); 1842680SN/A checkerTC->setIntReg(reg_idx, val); 1852315SN/A } 1862315SN/A 1872669SN/A void setFloatReg(int reg_idx, FloatReg val) 1882315SN/A { 1892680SN/A actualTC->setFloatReg(reg_idx, val); 1902680SN/A checkerTC->setFloatReg(reg_idx, val); 1912315SN/A } 1922315SN/A 1932669SN/A void setFloatRegBits(int reg_idx, FloatRegBits val) 1942669SN/A { 1952680SN/A actualTC->setFloatRegBits(reg_idx, val); 1962680SN/A checkerTC->setFloatRegBits(reg_idx, val); 1972315SN/A } 1982315SN/A 1992680SN/A uint64_t readPC() { return actualTC->readPC(); } 2002315SN/A 2012315SN/A void setPC(uint64_t val) 2022315SN/A { 2032680SN/A actualTC->setPC(val); 2042680SN/A checkerTC->setPC(val); 2052315SN/A checkerCPU->recordPCChange(val); 2062315SN/A } 2072315SN/A 2082680SN/A uint64_t readNextPC() { return actualTC->readNextPC(); } 2092315SN/A 2102315SN/A void setNextPC(uint64_t val) 2112315SN/A { 2122680SN/A actualTC->setNextPC(val); 2132680SN/A checkerTC->setNextPC(val); 2142315SN/A checkerCPU->recordNextPCChange(val); 2152315SN/A } 2162315SN/A 2172680SN/A uint64_t readNextNPC() { return actualTC->readNextNPC(); } 2182669SN/A 2192669SN/A void setNextNPC(uint64_t val) 2202669SN/A { 2212680SN/A actualTC->setNextNPC(val); 2222680SN/A checkerTC->setNextNPC(val); 2232669SN/A checkerCPU->recordNextPCChange(val); 2242669SN/A } 2252669SN/A 2264172Ssaidi@eecs.umich.edu MiscReg readMiscRegNoEffect(int misc_reg) 2274172Ssaidi@eecs.umich.edu { return actualTC->readMiscRegNoEffect(misc_reg); } 2284172Ssaidi@eecs.umich.edu 2292315SN/A MiscReg readMiscReg(int misc_reg) 2302680SN/A { return actualTC->readMiscReg(misc_reg); } 2312315SN/A 2324172Ssaidi@eecs.umich.edu void setMiscRegNoEffect(int misc_reg, const MiscReg &val) 2334172Ssaidi@eecs.umich.edu { 2344172Ssaidi@eecs.umich.edu checkerTC->setMiscRegNoEffect(misc_reg, val); 2354172Ssaidi@eecs.umich.edu actualTC->setMiscRegNoEffect(misc_reg, val); 2364172Ssaidi@eecs.umich.edu } 2372315SN/A 2383468Sgblack@eecs.umich.edu void setMiscReg(int misc_reg, const MiscReg &val) 2392315SN/A { 2402680SN/A checkerTC->setMiscReg(misc_reg, val); 2413468Sgblack@eecs.umich.edu actualTC->setMiscReg(misc_reg, val); 2422315SN/A } 2432315SN/A 2442315SN/A unsigned readStCondFailures() 2452680SN/A { return actualTC->readStCondFailures(); } 2462315SN/A 2472315SN/A void setStCondFailures(unsigned sc_failures) 2482315SN/A { 2492680SN/A checkerTC->setStCondFailures(sc_failures); 2502680SN/A actualTC->setStCondFailures(sc_failures); 2512315SN/A } 2522315SN/A 2532315SN/A // @todo: Fix this! 2542680SN/A bool misspeculating() { return actualTC->misspeculating(); } 2552315SN/A 2562315SN/A#if !FULL_SYSTEM 2572680SN/A Counter readFuncExeInst() { return actualTC->readFuncExeInst(); } 2582315SN/A#endif 2592315SN/A}; 2602315SN/A 2612315SN/A#endif // __CPU_CHECKER_EXEC_CONTEXT_HH__ 262