thread_context.hh revision 4997
12330SN/A/* 22330SN/A * Copyright (c) 2006 The Regents of The University of Michigan 32330SN/A * All rights reserved. 42330SN/A * 52330SN/A * Redistribution and use in source and binary forms, with or without 62330SN/A * modification, are permitted provided that the following conditions are 72330SN/A * met: redistributions of source code must retain the above copyright 82330SN/A * notice, this list of conditions and the following disclaimer; 92330SN/A * redistributions in binary form must reproduce the above copyright 102330SN/A * notice, this list of conditions and the following disclaimer in the 112330SN/A * documentation and/or other materials provided with the distribution; 122330SN/A * neither the name of the copyright holders nor the names of its 132330SN/A * contributors may be used to endorse or promote products derived from 142330SN/A * this software without specific prior written permission. 152330SN/A * 162330SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172330SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182330SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192330SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202330SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212330SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222330SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232330SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242330SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252330SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262330SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272689Sktlim@umich.edu * 282689Sktlim@umich.edu * Authors: Kevin Lim 292330SN/A */ 302330SN/A 312683Sktlim@umich.edu#ifndef __CPU_CHECKER_THREAD_CONTEXT_HH__ 322683Sktlim@umich.edu#define __CPU_CHECKER_THREAD_CONTEXT_HH__ 332315SN/A 342972Sgblack@eecs.umich.edu#include "arch/types.hh" 352315SN/A#include "cpu/checker/cpu.hh" 362683Sktlim@umich.edu#include "cpu/simple_thread.hh" 372680SN/A#include "cpu/thread_context.hh" 382315SN/A 392315SN/Aclass EndQuiesceEvent; 403548Sgblack@eecs.umich.edunamespace TheISA { 413548Sgblack@eecs.umich.edu namespace Kernel { 423548Sgblack@eecs.umich.edu class Statistics; 433548Sgblack@eecs.umich.edu }; 442330SN/A}; 452315SN/A 462350SN/A/** 472680SN/A * Derived ThreadContext class for use with the Checker. The template 482680SN/A * parameter is the ThreadContext class used by the specific CPU being 492683Sktlim@umich.edu * verified. This CheckerThreadContext is then used by the main CPU 502683Sktlim@umich.edu * in place of its usual ThreadContext class. It handles updating the 512683Sktlim@umich.edu * checker's state any time state is updated externally through the 522683Sktlim@umich.edu * ThreadContext. 532350SN/A */ 542680SN/Atemplate <class TC> 552680SN/Aclass CheckerThreadContext : public ThreadContext 562315SN/A{ 572315SN/A public: 582680SN/A CheckerThreadContext(TC *actual_tc, 592683Sktlim@umich.edu CheckerCPU *checker_cpu) 602683Sktlim@umich.edu : actualTC(actual_tc), checkerTC(checker_cpu->thread), 612330SN/A checkerCPU(checker_cpu) 622315SN/A { } 632315SN/A 642315SN/A private: 652683Sktlim@umich.edu /** The main CPU's ThreadContext, or class that implements the 662683Sktlim@umich.edu * ThreadContext interface. */ 672680SN/A TC *actualTC; 682683Sktlim@umich.edu /** The checker's own SimpleThread. Will be updated any time 692683Sktlim@umich.edu * anything uses this ThreadContext to externally update a 702683Sktlim@umich.edu * thread's state. */ 712683Sktlim@umich.edu SimpleThread *checkerTC; 722683Sktlim@umich.edu /** Pointer to the checker CPU. */ 732315SN/A CheckerCPU *checkerCPU; 742315SN/A 752315SN/A public: 762315SN/A 772680SN/A BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); } 782315SN/A 792315SN/A void setCpuId(int id) 802315SN/A { 812680SN/A actualTC->setCpuId(id); 822680SN/A checkerTC->setCpuId(id); 832315SN/A } 842315SN/A 852680SN/A int readCpuId() { return actualTC->readCpuId(); } 862315SN/A 874997Sgblack@eecs.umich.edu TheISA::ITB *getITBPtr() { return actualTC->getITBPtr(); } 884997Sgblack@eecs.umich.edu 894997Sgblack@eecs.umich.edu TheISA::DTB *getDTBPtr() { return actualTC->getDTBPtr(); } 904997Sgblack@eecs.umich.edu 912315SN/A#if FULL_SYSTEM 922680SN/A System *getSystemPtr() { return actualTC->getSystemPtr(); } 932315SN/A 942680SN/A PhysicalMemory *getPhysMemPtr() { return actualTC->getPhysMemPtr(); } 952315SN/A 963548Sgblack@eecs.umich.edu TheISA::Kernel::Statistics *getKernelStats() 973548Sgblack@eecs.umich.edu { return actualTC->getKernelStats(); } 982690Sktlim@umich.edu 992690Sktlim@umich.edu FunctionalPort *getPhysPort() { return actualTC->getPhysPort(); } 1002690Sktlim@umich.edu 1012690Sktlim@umich.edu VirtualPort *getVirtPort(ThreadContext *tc = NULL) 1022690Sktlim@umich.edu { return actualTC->getVirtPort(); } 1032690Sktlim@umich.edu 1042690Sktlim@umich.edu void delVirtPort(VirtualPort *vp) { actualTC->delVirtPort(vp); } 1052315SN/A#else 1062690Sktlim@umich.edu TranslatingPort *getMemPort() { return actualTC->getMemPort(); } 1072690Sktlim@umich.edu 1082680SN/A Process *getProcessPtr() { return actualTC->getProcessPtr(); } 1092315SN/A#endif 1102315SN/A 1112680SN/A Status status() const { return actualTC->status(); } 1122315SN/A 1132315SN/A void setStatus(Status new_status) 1142330SN/A { 1152680SN/A actualTC->setStatus(new_status); 1162680SN/A checkerTC->setStatus(new_status); 1172330SN/A } 1182315SN/A 1192315SN/A /// Set the status to Active. Optional delay indicates number of 1202315SN/A /// cycles to wait before beginning execution. 1212680SN/A void activate(int delay = 1) { actualTC->activate(delay); } 1222315SN/A 1232315SN/A /// Set the status to Suspended. 1242680SN/A void suspend() { actualTC->suspend(); } 1252315SN/A 1262315SN/A /// Set the status to Unallocated. 1272887Sktlim@umich.edu void deallocate(int delay = 0) { actualTC->deallocate(delay); } 1282315SN/A 1292315SN/A /// Set the status to Halted. 1302680SN/A void halt() { actualTC->halt(); } 1312315SN/A 1322315SN/A#if FULL_SYSTEM 1332680SN/A void dumpFuncProfile() { actualTC->dumpFuncProfile(); } 1342315SN/A#endif 1352315SN/A 1362680SN/A void takeOverFrom(ThreadContext *oldContext) 1372315SN/A { 1382680SN/A actualTC->takeOverFrom(oldContext); 1393225Sktlim@umich.edu checkerTC->copyState(oldContext); 1402315SN/A } 1412315SN/A 1422680SN/A void regStats(const std::string &name) { actualTC->regStats(name); } 1432315SN/A 1442680SN/A void serialize(std::ostream &os) { actualTC->serialize(os); } 1452315SN/A void unserialize(Checkpoint *cp, const std::string §ion) 1462680SN/A { actualTC->unserialize(cp, section); } 1472315SN/A 1482315SN/A#if FULL_SYSTEM 1492680SN/A EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); } 1502315SN/A 1512680SN/A Tick readLastActivate() { return actualTC->readLastActivate(); } 1522680SN/A Tick readLastSuspend() { return actualTC->readLastSuspend(); } 1532315SN/A 1542680SN/A void profileClear() { return actualTC->profileClear(); } 1552680SN/A void profileSample() { return actualTC->profileSample(); } 1562315SN/A#endif 1572315SN/A 1582680SN/A int getThreadNum() { return actualTC->getThreadNum(); } 1592315SN/A 1602315SN/A // @todo: Do I need this? 1612680SN/A MachInst getInst() { return actualTC->getInst(); } 1622315SN/A 1632315SN/A // @todo: Do I need this? 1642680SN/A void copyArchRegs(ThreadContext *tc) 1652315SN/A { 1662680SN/A actualTC->copyArchRegs(tc); 1672680SN/A checkerTC->copyArchRegs(tc); 1682315SN/A } 1692315SN/A 1702315SN/A void clearArchRegs() 1712315SN/A { 1722680SN/A actualTC->clearArchRegs(); 1732680SN/A checkerTC->clearArchRegs(); 1742315SN/A } 1752315SN/A 1762315SN/A // 1772315SN/A // New accessors for new decoder. 1782315SN/A // 1792315SN/A uint64_t readIntReg(int reg_idx) 1802680SN/A { return actualTC->readIntReg(reg_idx); } 1812315SN/A 1822669SN/A FloatReg readFloatReg(int reg_idx, int width) 1832680SN/A { return actualTC->readFloatReg(reg_idx, width); } 1842315SN/A 1852669SN/A FloatReg readFloatReg(int reg_idx) 1862680SN/A { return actualTC->readFloatReg(reg_idx); } 1872315SN/A 1882669SN/A FloatRegBits readFloatRegBits(int reg_idx, int width) 1892680SN/A { return actualTC->readFloatRegBits(reg_idx, width); } 1902669SN/A 1912669SN/A FloatRegBits readFloatRegBits(int reg_idx) 1922680SN/A { return actualTC->readFloatRegBits(reg_idx); } 1932315SN/A 1942315SN/A void setIntReg(int reg_idx, uint64_t val) 1952315SN/A { 1962680SN/A actualTC->setIntReg(reg_idx, val); 1972680SN/A checkerTC->setIntReg(reg_idx, val); 1982315SN/A } 1992315SN/A 2002669SN/A void setFloatReg(int reg_idx, FloatReg val, int width) 2012315SN/A { 2022680SN/A actualTC->setFloatReg(reg_idx, val, width); 2032680SN/A checkerTC->setFloatReg(reg_idx, val, width); 2042315SN/A } 2052315SN/A 2062669SN/A void setFloatReg(int reg_idx, FloatReg val) 2072315SN/A { 2082680SN/A actualTC->setFloatReg(reg_idx, val); 2092680SN/A checkerTC->setFloatReg(reg_idx, val); 2102315SN/A } 2112315SN/A 2122669SN/A void setFloatRegBits(int reg_idx, FloatRegBits val, int width) 2132315SN/A { 2142680SN/A actualTC->setFloatRegBits(reg_idx, val, width); 2152680SN/A checkerTC->setFloatRegBits(reg_idx, val, width); 2162669SN/A } 2172669SN/A 2182669SN/A void setFloatRegBits(int reg_idx, FloatRegBits val) 2192669SN/A { 2202680SN/A actualTC->setFloatRegBits(reg_idx, val); 2212680SN/A checkerTC->setFloatRegBits(reg_idx, val); 2222315SN/A } 2232315SN/A 2242680SN/A uint64_t readPC() { return actualTC->readPC(); } 2252315SN/A 2262315SN/A void setPC(uint64_t val) 2272315SN/A { 2282680SN/A actualTC->setPC(val); 2292680SN/A checkerTC->setPC(val); 2302315SN/A checkerCPU->recordPCChange(val); 2312315SN/A } 2322315SN/A 2332680SN/A uint64_t readNextPC() { return actualTC->readNextPC(); } 2342315SN/A 2352315SN/A void setNextPC(uint64_t val) 2362315SN/A { 2372680SN/A actualTC->setNextPC(val); 2382680SN/A checkerTC->setNextPC(val); 2392315SN/A checkerCPU->recordNextPCChange(val); 2402315SN/A } 2412315SN/A 2422680SN/A uint64_t readNextNPC() { return actualTC->readNextNPC(); } 2432669SN/A 2442669SN/A void setNextNPC(uint64_t val) 2452669SN/A { 2462680SN/A actualTC->setNextNPC(val); 2472680SN/A checkerTC->setNextNPC(val); 2482669SN/A checkerCPU->recordNextPCChange(val); 2492669SN/A } 2502669SN/A 2514172Ssaidi@eecs.umich.edu MiscReg readMiscRegNoEffect(int misc_reg) 2524172Ssaidi@eecs.umich.edu { return actualTC->readMiscRegNoEffect(misc_reg); } 2534172Ssaidi@eecs.umich.edu 2542315SN/A MiscReg readMiscReg(int misc_reg) 2552680SN/A { return actualTC->readMiscReg(misc_reg); } 2562315SN/A 2574172Ssaidi@eecs.umich.edu void setMiscRegNoEffect(int misc_reg, const MiscReg &val) 2584172Ssaidi@eecs.umich.edu { 2594172Ssaidi@eecs.umich.edu checkerTC->setMiscRegNoEffect(misc_reg, val); 2604172Ssaidi@eecs.umich.edu actualTC->setMiscRegNoEffect(misc_reg, val); 2614172Ssaidi@eecs.umich.edu } 2622315SN/A 2633468Sgblack@eecs.umich.edu void setMiscReg(int misc_reg, const MiscReg &val) 2642315SN/A { 2652680SN/A checkerTC->setMiscReg(misc_reg, val); 2663468Sgblack@eecs.umich.edu actualTC->setMiscReg(misc_reg, val); 2672315SN/A } 2682315SN/A 2692315SN/A unsigned readStCondFailures() 2702680SN/A { return actualTC->readStCondFailures(); } 2712315SN/A 2722315SN/A void setStCondFailures(unsigned sc_failures) 2732315SN/A { 2742680SN/A checkerTC->setStCondFailures(sc_failures); 2752680SN/A actualTC->setStCondFailures(sc_failures); 2762315SN/A } 2772315SN/A 2782315SN/A // @todo: Fix this! 2792680SN/A bool misspeculating() { return actualTC->misspeculating(); } 2802315SN/A 2812315SN/A#if !FULL_SYSTEM 2822680SN/A IntReg getSyscallArg(int i) { return actualTC->getSyscallArg(i); } 2832315SN/A 2842315SN/A // used to shift args for indirect syscall 2852315SN/A void setSyscallArg(int i, IntReg val) 2862315SN/A { 2872680SN/A checkerTC->setSyscallArg(i, val); 2882680SN/A actualTC->setSyscallArg(i, val); 2892315SN/A } 2902315SN/A 2912315SN/A void setSyscallReturn(SyscallReturn return_value) 2922315SN/A { 2932680SN/A checkerTC->setSyscallReturn(return_value); 2942680SN/A actualTC->setSyscallReturn(return_value); 2952315SN/A } 2962315SN/A 2972680SN/A Counter readFuncExeInst() { return actualTC->readFuncExeInst(); } 2982315SN/A#endif 2992972Sgblack@eecs.umich.edu void changeRegFileContext(TheISA::RegContextParam param, 3002972Sgblack@eecs.umich.edu TheISA::RegContextVal val) 3012669SN/A { 3022680SN/A actualTC->changeRegFileContext(param, val); 3032680SN/A checkerTC->changeRegFileContext(param, val); 3042669SN/A } 3052315SN/A}; 3062315SN/A 3072315SN/A#endif // __CPU_CHECKER_EXEC_CONTEXT_HH__ 308