thread_context.hh revision 13905
113996Sgiacomo.travaglini@arm.com/* 29525SAndreas.Sandberg@ARM.com * Copyright (c) 2011-2012, 2016-2018 ARM Limited 39525SAndreas.Sandberg@ARM.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 49525SAndreas.Sandberg@ARM.com * All rights reserved 59525SAndreas.Sandberg@ARM.com * 69525SAndreas.Sandberg@ARM.com * The license below extends only to copyright in the software and shall 79525SAndreas.Sandberg@ARM.com * not be construed as granting a license to any other intellectual 89525SAndreas.Sandberg@ARM.com * property including but not limited to intellectual property relating 99525SAndreas.Sandberg@ARM.com * to a hardware implementation of the functionality of the software 109525SAndreas.Sandberg@ARM.com * licensed hereunder. You may use the software subject to the license 119525SAndreas.Sandberg@ARM.com * terms below provided that you ensure that this notice is replicated 129525SAndreas.Sandberg@ARM.com * unmodified and in its entirety in all distributions of the software, 139525SAndreas.Sandberg@ARM.com * modified or unmodified, in source code or in binary form. 149525SAndreas.Sandberg@ARM.com * 159525SAndreas.Sandberg@ARM.com * Copyright (c) 2006 The Regents of The University of Michigan 169525SAndreas.Sandberg@ARM.com * All rights reserved. 179525SAndreas.Sandberg@ARM.com * 189525SAndreas.Sandberg@ARM.com * Redistribution and use in source and binary forms, with or without 199525SAndreas.Sandberg@ARM.com * modification, are permitted provided that the following conditions are 209525SAndreas.Sandberg@ARM.com * met: redistributions of source code must retain the above copyright 219525SAndreas.Sandberg@ARM.com * notice, this list of conditions and the following disclaimer; 229525SAndreas.Sandberg@ARM.com * redistributions in binary form must reproduce the above copyright 239525SAndreas.Sandberg@ARM.com * notice, this list of conditions and the following disclaimer in the 249525SAndreas.Sandberg@ARM.com * documentation and/or other materials provided with the distribution; 259525SAndreas.Sandberg@ARM.com * neither the name of the copyright holders nor the names of its 269525SAndreas.Sandberg@ARM.com * contributors may be used to endorse or promote products derived from 279525SAndreas.Sandberg@ARM.com * this software without specific prior written permission. 289525SAndreas.Sandberg@ARM.com * 299525SAndreas.Sandberg@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 309525SAndreas.Sandberg@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 319525SAndreas.Sandberg@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 329525SAndreas.Sandberg@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 339525SAndreas.Sandberg@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 349525SAndreas.Sandberg@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 359525SAndreas.Sandberg@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 369525SAndreas.Sandberg@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 379525SAndreas.Sandberg@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 389525SAndreas.Sandberg@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 399525SAndreas.Sandberg@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 4013591Sciro.santilli@arm.com * 4110749Smatt.evans@arm.com * Authors: Kevin Lim 429525SAndreas.Sandberg@ARM.com */ 4313996Sgiacomo.travaglini@arm.com 4413665Sandreas.sandberg@arm.com#ifndef __CPU_CHECKER_THREAD_CONTEXT_HH__ 459525SAndreas.Sandberg@ARM.com#define __CPU_CHECKER_THREAD_CONTEXT_HH__ 469525SAndreas.Sandberg@ARM.com 479525SAndreas.Sandberg@ARM.com#include "arch/types.hh" 489525SAndreas.Sandberg@ARM.com#include "config/the_isa.hh" 499525SAndreas.Sandberg@ARM.com#include "cpu/checker/cpu.hh" 509525SAndreas.Sandberg@ARM.com#include "cpu/simple_thread.hh" 5114152Sgiacomo.travaglini@arm.com#include "cpu/thread_context.hh" 5214152Sgiacomo.travaglini@arm.com#include "debug/Checker.hh" 5314152Sgiacomo.travaglini@arm.com 549525SAndreas.Sandberg@ARM.comclass EndQuiesceEvent; 559525SAndreas.Sandberg@ARM.comnamespace Kernel { 5613505Sgiacomo.travaglini@arm.com class Statistics; 5713505Sgiacomo.travaglini@arm.com}; 5813505Sgiacomo.travaglini@arm.comnamespace TheISA { 5913505Sgiacomo.travaglini@arm.com class Decoder; 6013505Sgiacomo.travaglini@arm.com}; 6113505Sgiacomo.travaglini@arm.com 6213505Sgiacomo.travaglini@arm.com/** 6313505Sgiacomo.travaglini@arm.com * Derived ThreadContext class for use with the Checker. The template 6413505Sgiacomo.travaglini@arm.com * parameter is the ThreadContext class used by the specific CPU being 6514152Sgiacomo.travaglini@arm.com * verified. This CheckerThreadContext is then used by the main CPU 6614152Sgiacomo.travaglini@arm.com * in place of its usual ThreadContext class. It handles updating the 6714152Sgiacomo.travaglini@arm.com * checker's state any time state is updated externally through the 6814152Sgiacomo.travaglini@arm.com * ThreadContext. 6914152Sgiacomo.travaglini@arm.com */ 7014152Sgiacomo.travaglini@arm.comtemplate <class TC> 7114152Sgiacomo.travaglini@arm.comclass CheckerThreadContext : public ThreadContext 7214152Sgiacomo.travaglini@arm.com{ 7314152Sgiacomo.travaglini@arm.com public: 7414152Sgiacomo.travaglini@arm.com CheckerThreadContext(TC *actual_tc, 7512739Sandreas.sandberg@arm.com CheckerCPU *checker_cpu) 7612739Sandreas.sandberg@arm.com : actualTC(actual_tc), checkerTC(checker_cpu->thread), 7712739Sandreas.sandberg@arm.com checkerCPU(checker_cpu) 7812974Sgiacomo.travaglini@arm.com { } 7912739Sandreas.sandberg@arm.com 8012739Sandreas.sandberg@arm.com private: 8112739Sandreas.sandberg@arm.com /** The main CPU's ThreadContext, or class that implements the 8212739Sandreas.sandberg@arm.com * ThreadContext interface. */ 8312739Sandreas.sandberg@arm.com TC *actualTC; 8412739Sandreas.sandberg@arm.com /** The checker's own SimpleThread. Will be updated any time 8512739Sandreas.sandberg@arm.com * anything uses this ThreadContext to externally update a 8612739Sandreas.sandberg@arm.com * thread's state. */ 8712974Sgiacomo.travaglini@arm.com SimpleThread *checkerTC; 8812739Sandreas.sandberg@arm.com /** Pointer to the checker CPU. */ 8912739Sandreas.sandberg@arm.com CheckerCPU *checkerCPU; 9012739Sandreas.sandberg@arm.com 9112739Sandreas.sandberg@arm.com public: 9212974Sgiacomo.travaglini@arm.com 9312739Sandreas.sandberg@arm.com BaseCPU *getCpuPtr() override { return actualTC->getCpuPtr(); } 9413014Sciro.santilli@arm.com 9513014Sciro.santilli@arm.com uint32_t socketId() const override { return actualTC->socketId(); } 9613014Sciro.santilli@arm.com 979525SAndreas.Sandberg@ARM.com int cpuId() const override { return actualTC->cpuId(); } 9813013Sciro.santilli@arm.com 9913013Sciro.santilli@arm.com ContextID contextId() const override { return actualTC->contextId(); } 10013013Sciro.santilli@arm.com 1019525SAndreas.Sandberg@ARM.com void 1029525SAndreas.Sandberg@ARM.com setContextId(ContextID id) override 1039525SAndreas.Sandberg@ARM.com { 1049525SAndreas.Sandberg@ARM.com actualTC->setContextId(id); 10511652SCurtis.Dunham@arm.com checkerTC->setContextId(id); 10610749Smatt.evans@arm.com } 10713505Sgiacomo.travaglini@arm.com 10813505Sgiacomo.travaglini@arm.com /** Returns this thread's ID number. */ 10913505Sgiacomo.travaglini@arm.com int threadId() const override { return actualTC->threadId(); } 11013505Sgiacomo.travaglini@arm.com void 11113505Sgiacomo.travaglini@arm.com setThreadId(int id) override 11213505Sgiacomo.travaglini@arm.com { 11313505Sgiacomo.travaglini@arm.com checkerTC->setThreadId(id); 11413505Sgiacomo.travaglini@arm.com actualTC->setThreadId(id); 11513505Sgiacomo.travaglini@arm.com } 11613505Sgiacomo.travaglini@arm.com 11713505Sgiacomo.travaglini@arm.com BaseTLB *getITBPtr() override { return actualTC->getITBPtr(); } 11813505Sgiacomo.travaglini@arm.com 11913505Sgiacomo.travaglini@arm.com BaseTLB *getDTBPtr() override { return actualTC->getDTBPtr(); } 12010749Smatt.evans@arm.com 12110749Smatt.evans@arm.com CheckerCPU * 12210749Smatt.evans@arm.com getCheckerCpuPtr() override 12310749Smatt.evans@arm.com { 12410749Smatt.evans@arm.com return checkerCPU; 12510749Smatt.evans@arm.com } 12610749Smatt.evans@arm.com 12710749Smatt.evans@arm.com TheISA::ISA *getIsaPtr() override { return actualTC->getIsaPtr(); } 12810749Smatt.evans@arm.com 12910749Smatt.evans@arm.com TheISA::Decoder * 13010749Smatt.evans@arm.com getDecoderPtr() override 13110749Smatt.evans@arm.com { 13210749Smatt.evans@arm.com return actualTC->getDecoderPtr(); 13310749Smatt.evans@arm.com } 13413504Sgiacomo.travaglini@arm.com 13513504Sgiacomo.travaglini@arm.com System *getSystemPtr() override { return actualTC->getSystemPtr(); } 13613504Sgiacomo.travaglini@arm.com 13713504Sgiacomo.travaglini@arm.com ::Kernel::Statistics * 13813504Sgiacomo.travaglini@arm.com getKernelStats() override 13913504Sgiacomo.travaglini@arm.com { 14013504Sgiacomo.travaglini@arm.com return actualTC->getKernelStats(); 14113504Sgiacomo.travaglini@arm.com } 14213504Sgiacomo.travaglini@arm.com 14313504Sgiacomo.travaglini@arm.com Process *getProcessPtr() override { return actualTC->getProcessPtr(); } 14413814Sgiacomo.travaglini@arm.com 14513504Sgiacomo.travaglini@arm.com void setProcessPtr(Process *p) override { actualTC->setProcessPtr(p); } 14613505Sgiacomo.travaglini@arm.com 14713505Sgiacomo.travaglini@arm.com PortProxy &getPhysProxy() override { return actualTC->getPhysProxy(); } 14813505Sgiacomo.travaglini@arm.com 14913505Sgiacomo.travaglini@arm.com FSTranslatingPortProxy & 15013504Sgiacomo.travaglini@arm.com getVirtProxy() override 15113504Sgiacomo.travaglini@arm.com { 15213504Sgiacomo.travaglini@arm.com return actualTC->getVirtProxy(); 15313504Sgiacomo.travaglini@arm.com } 15413504Sgiacomo.travaglini@arm.com 15513504Sgiacomo.travaglini@arm.com void 15614152Sgiacomo.travaglini@arm.com initMemProxies(ThreadContext *tc) override 15714152Sgiacomo.travaglini@arm.com { 15813504Sgiacomo.travaglini@arm.com actualTC->initMemProxies(tc); 15913504Sgiacomo.travaglini@arm.com } 16013504Sgiacomo.travaglini@arm.com 16113504Sgiacomo.travaglini@arm.com void 16213504Sgiacomo.travaglini@arm.com connectMemPorts(ThreadContext *tc) 16313504Sgiacomo.travaglini@arm.com { 16413504Sgiacomo.travaglini@arm.com actualTC->connectMemPorts(tc); 16513504Sgiacomo.travaglini@arm.com } 16613504Sgiacomo.travaglini@arm.com 16713504Sgiacomo.travaglini@arm.com SETranslatingPortProxy & 16813504Sgiacomo.travaglini@arm.com getMemProxy() override 16913504Sgiacomo.travaglini@arm.com { 17013504Sgiacomo.travaglini@arm.com return actualTC->getMemProxy(); 17113504Sgiacomo.travaglini@arm.com } 17213814Sgiacomo.travaglini@arm.com 17313504Sgiacomo.travaglini@arm.com /** Executes a syscall in SE mode. */ 17413504Sgiacomo.travaglini@arm.com void 17513504Sgiacomo.travaglini@arm.com syscall(int64_t callnum, Fault *fault) override 17613504Sgiacomo.travaglini@arm.com { 17713531Sjairo.balart@metempsy.com return actualTC->syscall(callnum, fault); 17813996Sgiacomo.travaglini@arm.com } 17913996Sgiacomo.travaglini@arm.com 18013996Sgiacomo.travaglini@arm.com Status status() const override { return actualTC->status(); } 18113996Sgiacomo.travaglini@arm.com 18213996Sgiacomo.travaglini@arm.com void 18313996Sgiacomo.travaglini@arm.com setStatus(Status new_status) override 18413996Sgiacomo.travaglini@arm.com { 18513996Sgiacomo.travaglini@arm.com actualTC->setStatus(new_status); 18613996Sgiacomo.travaglini@arm.com checkerTC->setStatus(new_status); 18713996Sgiacomo.travaglini@arm.com } 18813996Sgiacomo.travaglini@arm.com 18913996Sgiacomo.travaglini@arm.com /// Set the status to Active. 19013531Sjairo.balart@metempsy.com void activate() override { actualTC->activate(); } 19113531Sjairo.balart@metempsy.com 19213531Sjairo.balart@metempsy.com /// Set the status to Suspended. 19313531Sjairo.balart@metempsy.com void suspend() override { actualTC->suspend(); } 19414152Sgiacomo.travaglini@arm.com 19514154Sgiacomo.travaglini@arm.com /// Set the status to Halted. 19614152Sgiacomo.travaglini@arm.com void halt() override { actualTC->halt(); } 19713996Sgiacomo.travaglini@arm.com 19813996Sgiacomo.travaglini@arm.com void dumpFuncProfile() override { actualTC->dumpFuncProfile(); } 19913880Sgiacomo.travaglini@arm.com 20013531Sjairo.balart@metempsy.com void 20113880Sgiacomo.travaglini@arm.com takeOverFrom(ThreadContext *oldContext) override 20213531Sjairo.balart@metempsy.com { 20313531Sjairo.balart@metempsy.com actualTC->takeOverFrom(oldContext); 20413531Sjairo.balart@metempsy.com checkerTC->copyState(oldContext); 20513531Sjairo.balart@metempsy.com } 20613826Sgiacomo.travaglini@arm.com 20713826Sgiacomo.travaglini@arm.com void 20813826Sgiacomo.travaglini@arm.com regStats(const std::string &name) override 20913826Sgiacomo.travaglini@arm.com { 21013826Sgiacomo.travaglini@arm.com actualTC->regStats(name); 21113877Sgiacomo.travaglini@arm.com checkerTC->regStats(name); 21213877Sgiacomo.travaglini@arm.com } 21313877Sgiacomo.travaglini@arm.com 21413877Sgiacomo.travaglini@arm.com EndQuiesceEvent * 21513878Sgiacomo.travaglini@arm.com getQuiesceEvent() override 21613878Sgiacomo.travaglini@arm.com { 21714154Sgiacomo.travaglini@arm.com return actualTC->getQuiesceEvent(); 21814154Sgiacomo.travaglini@arm.com } 21914154Sgiacomo.travaglini@arm.com 22014154Sgiacomo.travaglini@arm.com Tick readLastActivate() override { return actualTC->readLastActivate(); } 22114154Sgiacomo.travaglini@arm.com Tick readLastSuspend() override { return actualTC->readLastSuspend(); } 22214154Sgiacomo.travaglini@arm.com 22314154Sgiacomo.travaglini@arm.com void profileClear() override { return actualTC->profileClear(); } 22414154Sgiacomo.travaglini@arm.com void profileSample() override { return actualTC->profileSample(); } 22514154Sgiacomo.travaglini@arm.com 22614154Sgiacomo.travaglini@arm.com // @todo: Do I need this? 22714154Sgiacomo.travaglini@arm.com void 22814154Sgiacomo.travaglini@arm.com copyArchRegs(ThreadContext *tc) override 22914154Sgiacomo.travaglini@arm.com { 23014154Sgiacomo.travaglini@arm.com actualTC->copyArchRegs(tc); 23114154Sgiacomo.travaglini@arm.com checkerTC->copyArchRegs(tc); 23214154Sgiacomo.travaglini@arm.com } 23314154Sgiacomo.travaglini@arm.com 23414154Sgiacomo.travaglini@arm.com void 23514154Sgiacomo.travaglini@arm.com clearArchRegs() override 23614154Sgiacomo.travaglini@arm.com { 23714154Sgiacomo.travaglini@arm.com actualTC->clearArchRegs(); 23814154Sgiacomo.travaglini@arm.com checkerTC->clearArchRegs(); 23914154Sgiacomo.travaglini@arm.com } 24014173Sgiacomo.travaglini@arm.com 24114173Sgiacomo.travaglini@arm.com // 24214173Sgiacomo.travaglini@arm.com // New accessors for new decoder. 24314173Sgiacomo.travaglini@arm.com // 24414154Sgiacomo.travaglini@arm.com RegVal 24514154Sgiacomo.travaglini@arm.com readIntReg(RegIndex reg_idx) const override 24614154Sgiacomo.travaglini@arm.com { 24714154Sgiacomo.travaglini@arm.com return actualTC->readIntReg(reg_idx); 24814154Sgiacomo.travaglini@arm.com } 24914154Sgiacomo.travaglini@arm.com 25014154Sgiacomo.travaglini@arm.com RegVal 25114154Sgiacomo.travaglini@arm.com readFloatReg(RegIndex reg_idx) const override 25214154Sgiacomo.travaglini@arm.com { 25314154Sgiacomo.travaglini@arm.com return actualTC->readFloatReg(reg_idx); 25414154Sgiacomo.travaglini@arm.com } 25514154Sgiacomo.travaglini@arm.com 25614154Sgiacomo.travaglini@arm.com const VecRegContainer & 257 readVecReg (const RegId ®) const override 258 { 259 return actualTC->readVecReg(reg); 260 } 261 262 /** 263 * Read vector register for modification, hierarchical indexing. 264 */ 265 VecRegContainer & 266 getWritableVecReg (const RegId ®) override 267 { 268 return actualTC->getWritableVecReg(reg); 269 } 270 271 /** Vector Register Lane Interfaces. */ 272 /** @{ */ 273 /** Reads source vector 8bit operand. */ 274 ConstVecLane8 275 readVec8BitLaneReg(const RegId ®) const override 276 { 277 return actualTC->readVec8BitLaneReg(reg); 278 } 279 280 /** Reads source vector 16bit operand. */ 281 ConstVecLane16 282 readVec16BitLaneReg(const RegId ®) const override 283 { 284 return actualTC->readVec16BitLaneReg(reg); 285 } 286 287 /** Reads source vector 32bit operand. */ 288 ConstVecLane32 289 readVec32BitLaneReg(const RegId ®) const override 290 { 291 return actualTC->readVec32BitLaneReg(reg); 292 } 293 294 /** Reads source vector 64bit operand. */ 295 ConstVecLane64 296 readVec64BitLaneReg(const RegId ®) const override 297 { 298 return actualTC->readVec64BitLaneReg(reg); 299 } 300 301 /** Write a lane of the destination vector register. */ 302 virtual void 303 setVecLane(const RegId ®, 304 const LaneData<LaneSize::Byte> &val) override 305 { 306 return actualTC->setVecLane(reg, val); 307 } 308 virtual void 309 setVecLane(const RegId ®, 310 const LaneData<LaneSize::TwoByte> &val) override 311 { 312 return actualTC->setVecLane(reg, val); 313 } 314 virtual void 315 setVecLane(const RegId ®, 316 const LaneData<LaneSize::FourByte> &val) override 317 { 318 return actualTC->setVecLane(reg, val); 319 } 320 virtual void 321 setVecLane(const RegId ®, 322 const LaneData<LaneSize::EightByte> &val) override 323 { 324 return actualTC->setVecLane(reg, val); 325 } 326 /** @} */ 327 328 const VecElem & 329 readVecElem(const RegId& reg) const override 330 { 331 return actualTC->readVecElem(reg); 332 } 333 334 const VecPredRegContainer & 335 readVecPredReg(const RegId& reg) const override 336 { 337 return actualTC->readVecPredReg(reg); 338 } 339 340 VecPredRegContainer & 341 getWritableVecPredReg(const RegId& reg) override 342 { 343 return actualTC->getWritableVecPredReg(reg); 344 } 345 346 RegVal 347 readCCReg(RegIndex reg_idx) const override 348 { 349 return actualTC->readCCReg(reg_idx); 350 } 351 352 void 353 setIntReg(RegIndex reg_idx, RegVal val) override 354 { 355 actualTC->setIntReg(reg_idx, val); 356 checkerTC->setIntReg(reg_idx, val); 357 } 358 359 void 360 setFloatReg(RegIndex reg_idx, RegVal val) override 361 { 362 actualTC->setFloatReg(reg_idx, val); 363 checkerTC->setFloatReg(reg_idx, val); 364 } 365 366 void 367 setVecReg(const RegId& reg, const VecRegContainer& val) override 368 { 369 actualTC->setVecReg(reg, val); 370 checkerTC->setVecReg(reg, val); 371 } 372 373 void 374 setVecElem(const RegId& reg, const VecElem& val) override 375 { 376 actualTC->setVecElem(reg, val); 377 checkerTC->setVecElem(reg, val); 378 } 379 380 void 381 setVecPredReg(const RegId& reg, const VecPredRegContainer& val) override 382 { 383 actualTC->setVecPredReg(reg, val); 384 checkerTC->setVecPredReg(reg, val); 385 } 386 387 void 388 setCCReg(RegIndex reg_idx, RegVal val) override 389 { 390 actualTC->setCCReg(reg_idx, val); 391 checkerTC->setCCReg(reg_idx, val); 392 } 393 394 /** Reads this thread's PC state. */ 395 TheISA::PCState pcState() const override { return actualTC->pcState(); } 396 397 /** Sets this thread's PC state. */ 398 void 399 pcState(const TheISA::PCState &val) override 400 { 401 DPRINTF(Checker, "Changing PC to %s, old PC %s\n", 402 val, checkerTC->pcState()); 403 checkerTC->pcState(val); 404 checkerCPU->recordPCChange(val); 405 return actualTC->pcState(val); 406 } 407 408 void 409 setNPC(Addr val) 410 { 411 checkerTC->setNPC(val); 412 actualTC->setNPC(val); 413 } 414 415 void 416 pcStateNoRecord(const TheISA::PCState &val) override 417 { 418 return actualTC->pcState(val); 419 } 420 421 /** Reads this thread's PC. */ 422 Addr instAddr() const override { return actualTC->instAddr(); } 423 424 /** Reads this thread's next PC. */ 425 Addr nextInstAddr() const override { return actualTC->nextInstAddr(); } 426 427 /** Reads this thread's next PC. */ 428 MicroPC microPC() const override { return actualTC->microPC(); } 429 430 RegVal 431 readMiscRegNoEffect(RegIndex misc_reg) const override 432 { 433 return actualTC->readMiscRegNoEffect(misc_reg); 434 } 435 436 RegVal 437 readMiscReg(RegIndex misc_reg) override 438 { 439 return actualTC->readMiscReg(misc_reg); 440 } 441 442 void 443 setMiscRegNoEffect(RegIndex misc_reg, RegVal val) override 444 { 445 DPRINTF(Checker, "Setting misc reg with no effect: %d to both Checker" 446 " and O3..\n", misc_reg); 447 checkerTC->setMiscRegNoEffect(misc_reg, val); 448 actualTC->setMiscRegNoEffect(misc_reg, val); 449 } 450 451 void 452 setMiscReg(RegIndex misc_reg, RegVal val) override 453 { 454 DPRINTF(Checker, "Setting misc reg with effect: %d to both Checker" 455 " and O3..\n", misc_reg); 456 checkerTC->setMiscReg(misc_reg, val); 457 actualTC->setMiscReg(misc_reg, val); 458 } 459 460 RegId 461 flattenRegId(const RegId& regId) const override 462 { 463 return actualTC->flattenRegId(regId); 464 } 465 466 unsigned 467 readStCondFailures() const override 468 { 469 return actualTC->readStCondFailures(); 470 } 471 472 void 473 setStCondFailures(unsigned sc_failures) override 474 { 475 actualTC->setStCondFailures(sc_failures); 476 } 477 478 Counter 479 readFuncExeInst() const override 480 { 481 return actualTC->readFuncExeInst(); 482 } 483 484 RegVal 485 readIntRegFlat(RegIndex idx) const override 486 { 487 return actualTC->readIntRegFlat(idx); 488 } 489 490 void 491 setIntRegFlat(RegIndex idx, RegVal val) override 492 { 493 actualTC->setIntRegFlat(idx, val); 494 } 495 496 RegVal 497 readFloatRegFlat(RegIndex idx) const override 498 { 499 return actualTC->readFloatRegFlat(idx); 500 } 501 502 void 503 setFloatRegFlat(RegIndex idx, RegVal val) override 504 { 505 actualTC->setFloatRegFlat(idx, val); 506 } 507 508 const VecRegContainer & 509 readVecRegFlat(RegIndex idx) const override 510 { 511 return actualTC->readVecRegFlat(idx); 512 } 513 514 /** 515 * Read vector register for modification, flat indexing. 516 */ 517 VecRegContainer & 518 getWritableVecRegFlat(RegIndex idx) override 519 { 520 return actualTC->getWritableVecRegFlat(idx); 521 } 522 523 void 524 setVecRegFlat(RegIndex idx, const VecRegContainer& val) override 525 { 526 actualTC->setVecRegFlat(idx, val); 527 } 528 529 const VecElem & 530 readVecElemFlat(RegIndex idx, const ElemIndex& elem_idx) const override 531 { 532 return actualTC->readVecElemFlat(idx, elem_idx); 533 } 534 535 void 536 setVecElemFlat(RegIndex idx, 537 const ElemIndex& elem_idx, const VecElem& val) override 538 { 539 actualTC->setVecElemFlat(idx, elem_idx, val); 540 } 541 542 const VecPredRegContainer & 543 readVecPredRegFlat(RegIndex idx) const override 544 { 545 return actualTC->readVecPredRegFlat(idx); 546 } 547 548 VecPredRegContainer & 549 getWritableVecPredRegFlat(RegIndex idx) override 550 { 551 return actualTC->getWritableVecPredRegFlat(idx); 552 } 553 554 void 555 setVecPredRegFlat(RegIndex idx, const VecPredRegContainer& val) override 556 { 557 actualTC->setVecPredRegFlat(idx, val); 558 } 559 560 RegVal 561 readCCRegFlat(RegIndex idx) const override 562 { 563 return actualTC->readCCRegFlat(idx); 564 } 565 566 void 567 setCCRegFlat(RegIndex idx, RegVal val) override 568 { 569 actualTC->setCCRegFlat(idx, val); 570 } 571}; 572 573#endif // __CPU_CHECKER_EXEC_CONTEXT_HH__ 574