thread_context.hh revision 10190
12330SN/A/* 29426SAndreas.Sandberg@ARM.com * Copyright (c) 2011-2012 ARM Limited 39920Syasuko.eckert@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 48733Sgeoffrey.blake@arm.com * All rights reserved 58733Sgeoffrey.blake@arm.com * 68733Sgeoffrey.blake@arm.com * The license below extends only to copyright in the software and shall 78733Sgeoffrey.blake@arm.com * not be construed as granting a license to any other intellectual 88733Sgeoffrey.blake@arm.com * property including but not limited to intellectual property relating 98733Sgeoffrey.blake@arm.com * to a hardware implementation of the functionality of the software 108733Sgeoffrey.blake@arm.com * licensed hereunder. You may use the software subject to the license 118733Sgeoffrey.blake@arm.com * terms below provided that you ensure that this notice is replicated 128733Sgeoffrey.blake@arm.com * unmodified and in its entirety in all distributions of the software, 138733Sgeoffrey.blake@arm.com * modified or unmodified, in source code or in binary form. 148733Sgeoffrey.blake@arm.com * 152330SN/A * Copyright (c) 2006 The Regents of The University of Michigan 162330SN/A * All rights reserved. 172330SN/A * 182330SN/A * Redistribution and use in source and binary forms, with or without 192330SN/A * modification, are permitted provided that the following conditions are 202330SN/A * met: redistributions of source code must retain the above copyright 212330SN/A * notice, this list of conditions and the following disclaimer; 222330SN/A * redistributions in binary form must reproduce the above copyright 232330SN/A * notice, this list of conditions and the following disclaimer in the 242330SN/A * documentation and/or other materials provided with the distribution; 252330SN/A * neither the name of the copyright holders nor the names of its 262330SN/A * contributors may be used to endorse or promote products derived from 272330SN/A * this software without specific prior written permission. 282330SN/A * 292330SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302330SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312330SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322330SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332330SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342330SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352330SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362330SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372330SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382330SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392330SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402689Sktlim@umich.edu * 412689Sktlim@umich.edu * Authors: Kevin Lim 422330SN/A */ 432330SN/A 442683Sktlim@umich.edu#ifndef __CPU_CHECKER_THREAD_CONTEXT_HH__ 452683Sktlim@umich.edu#define __CPU_CHECKER_THREAD_CONTEXT_HH__ 462315SN/A 472972Sgblack@eecs.umich.edu#include "arch/types.hh" 486658Snate@binkert.org#include "config/the_isa.hh" 492315SN/A#include "cpu/checker/cpu.hh" 502683Sktlim@umich.edu#include "cpu/simple_thread.hh" 512680SN/A#include "cpu/thread_context.hh" 528733Sgeoffrey.blake@arm.com#include "debug/Checker.hh" 532315SN/A 542315SN/Aclass EndQuiesceEvent; 553548Sgblack@eecs.umich.edunamespace TheISA { 563548Sgblack@eecs.umich.edu namespace Kernel { 573548Sgblack@eecs.umich.edu class Statistics; 583548Sgblack@eecs.umich.edu }; 599020Sgblack@eecs.umich.edu class Decoder; 602330SN/A}; 612315SN/A 622350SN/A/** 632680SN/A * Derived ThreadContext class for use with the Checker. The template 642680SN/A * parameter is the ThreadContext class used by the specific CPU being 652683Sktlim@umich.edu * verified. This CheckerThreadContext is then used by the main CPU 662683Sktlim@umich.edu * in place of its usual ThreadContext class. It handles updating the 672683Sktlim@umich.edu * checker's state any time state is updated externally through the 682683Sktlim@umich.edu * ThreadContext. 692350SN/A */ 702680SN/Atemplate <class TC> 712680SN/Aclass CheckerThreadContext : public ThreadContext 722315SN/A{ 732315SN/A public: 742680SN/A CheckerThreadContext(TC *actual_tc, 752683Sktlim@umich.edu CheckerCPU *checker_cpu) 762683Sktlim@umich.edu : actualTC(actual_tc), checkerTC(checker_cpu->thread), 772330SN/A checkerCPU(checker_cpu) 782315SN/A { } 792315SN/A 802315SN/A private: 812683Sktlim@umich.edu /** The main CPU's ThreadContext, or class that implements the 822683Sktlim@umich.edu * ThreadContext interface. */ 832680SN/A TC *actualTC; 842683Sktlim@umich.edu /** The checker's own SimpleThread. Will be updated any time 852683Sktlim@umich.edu * anything uses this ThreadContext to externally update a 862683Sktlim@umich.edu * thread's state. */ 872683Sktlim@umich.edu SimpleThread *checkerTC; 882683Sktlim@umich.edu /** Pointer to the checker CPU. */ 892315SN/A CheckerCPU *checkerCPU; 902315SN/A 912315SN/A public: 922315SN/A 932680SN/A BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); } 942315SN/A 9510190Sakash.bagdia@arm.com uint32_t socketId() const { return actualTC->socketId(); } 9610190Sakash.bagdia@arm.com 9710110Sandreas.hansson@arm.com int cpuId() const { return actualTC->cpuId(); } 988733Sgeoffrey.blake@arm.com 9910110Sandreas.hansson@arm.com int contextId() const { return actualTC->contextId(); } 1008733Sgeoffrey.blake@arm.com 1018733Sgeoffrey.blake@arm.com void setContextId(int id) 1022315SN/A { 1038733Sgeoffrey.blake@arm.com actualTC->setContextId(id); 1048733Sgeoffrey.blake@arm.com checkerTC->setContextId(id); 1052315SN/A } 1062315SN/A 1078733Sgeoffrey.blake@arm.com /** Returns this thread's ID number. */ 10810110Sandreas.hansson@arm.com int threadId() const { return actualTC->threadId(); } 1098733Sgeoffrey.blake@arm.com void setThreadId(int id) 1108733Sgeoffrey.blake@arm.com { 1118733Sgeoffrey.blake@arm.com checkerTC->setThreadId(id); 1128733Sgeoffrey.blake@arm.com actualTC->setThreadId(id); 1138733Sgeoffrey.blake@arm.com } 1142315SN/A 1156022Sgblack@eecs.umich.edu TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); } 1164997Sgblack@eecs.umich.edu 1176022Sgblack@eecs.umich.edu TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); } 1184997Sgblack@eecs.umich.edu 1198887Sgeoffrey.blake@arm.com CheckerCPU *getCheckerCpuPtr() 1208887Sgeoffrey.blake@arm.com { 1218887Sgeoffrey.blake@arm.com return checkerCPU; 1228887Sgeoffrey.blake@arm.com } 1238733Sgeoffrey.blake@arm.com 1249020Sgblack@eecs.umich.edu TheISA::Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); } 1258733Sgeoffrey.blake@arm.com 1262680SN/A System *getSystemPtr() { return actualTC->getSystemPtr(); } 1272315SN/A 1283548Sgblack@eecs.umich.edu TheISA::Kernel::Statistics *getKernelStats() 1293548Sgblack@eecs.umich.edu { return actualTC->getKernelStats(); } 1302690Sktlim@umich.edu 1317679Sgblack@eecs.umich.edu Process *getProcessPtr() { return actualTC->getProcessPtr(); } 1327679Sgblack@eecs.umich.edu 1338852Sandreas.hansson@arm.com PortProxy &getPhysProxy() { return actualTC->getPhysProxy(); } 1342690Sktlim@umich.edu 1358852Sandreas.hansson@arm.com FSTranslatingPortProxy &getVirtProxy() 1368706Sandreas.hansson@arm.com { return actualTC->getVirtProxy(); } 1378733Sgeoffrey.blake@arm.com 1388733Sgeoffrey.blake@arm.com void initMemProxies(ThreadContext *tc) 1398733Sgeoffrey.blake@arm.com { actualTC->initMemProxies(tc); } 1408733Sgeoffrey.blake@arm.com 1418733Sgeoffrey.blake@arm.com void connectMemPorts(ThreadContext *tc) 1428733Sgeoffrey.blake@arm.com { 1438733Sgeoffrey.blake@arm.com actualTC->connectMemPorts(tc); 1448733Sgeoffrey.blake@arm.com } 1458809Sgblack@eecs.umich.edu 1468852Sandreas.hansson@arm.com SETranslatingPortProxy &getMemProxy() { return actualTC->getMemProxy(); } 1472690Sktlim@umich.edu 1488733Sgeoffrey.blake@arm.com /** Executes a syscall in SE mode. */ 1498733Sgeoffrey.blake@arm.com void syscall(int64_t callnum) 1508733Sgeoffrey.blake@arm.com { return actualTC->syscall(callnum); } 1512315SN/A 1522680SN/A Status status() const { return actualTC->status(); } 1532315SN/A 1542315SN/A void setStatus(Status new_status) 1552330SN/A { 1562680SN/A actualTC->setStatus(new_status); 1572680SN/A checkerTC->setStatus(new_status); 1582330SN/A } 1592315SN/A 1602315SN/A /// Set the status to Active. Optional delay indicates number of 1612315SN/A /// cycles to wait before beginning execution. 1629180Sandreas.hansson@arm.com void activate(Cycles delay = Cycles(1)) 1639180Sandreas.hansson@arm.com { actualTC->activate(delay); } 1642315SN/A 1652315SN/A /// Set the status to Suspended. 1669180Sandreas.hansson@arm.com void suspend(Cycles delay) { actualTC->suspend(delay); } 1672315SN/A 1682315SN/A /// Set the status to Halted. 1699180Sandreas.hansson@arm.com void halt(Cycles delay) { actualTC->halt(delay); } 1702315SN/A 1712680SN/A void dumpFuncProfile() { actualTC->dumpFuncProfile(); } 1722315SN/A 1732680SN/A void takeOverFrom(ThreadContext *oldContext) 1742315SN/A { 1752680SN/A actualTC->takeOverFrom(oldContext); 1763225Sktlim@umich.edu checkerTC->copyState(oldContext); 1772315SN/A } 1782315SN/A 1798733Sgeoffrey.blake@arm.com void regStats(const std::string &name) 1808733Sgeoffrey.blake@arm.com { 1818733Sgeoffrey.blake@arm.com actualTC->regStats(name); 1828733Sgeoffrey.blake@arm.com checkerTC->regStats(name); 1838733Sgeoffrey.blake@arm.com } 1842315SN/A 1852680SN/A void serialize(std::ostream &os) { actualTC->serialize(os); } 1862315SN/A void unserialize(Checkpoint *cp, const std::string §ion) 1872680SN/A { actualTC->unserialize(cp, section); } 1882315SN/A 1892680SN/A EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); } 1902315SN/A 1912680SN/A Tick readLastActivate() { return actualTC->readLastActivate(); } 1922680SN/A Tick readLastSuspend() { return actualTC->readLastSuspend(); } 1932315SN/A 1942680SN/A void profileClear() { return actualTC->profileClear(); } 1952680SN/A void profileSample() { return actualTC->profileSample(); } 1962315SN/A 1972315SN/A // @todo: Do I need this? 1982680SN/A void copyArchRegs(ThreadContext *tc) 1992315SN/A { 2002680SN/A actualTC->copyArchRegs(tc); 2012680SN/A checkerTC->copyArchRegs(tc); 2022315SN/A } 2032315SN/A 2042315SN/A void clearArchRegs() 2052315SN/A { 2062680SN/A actualTC->clearArchRegs(); 2072680SN/A checkerTC->clearArchRegs(); 2082315SN/A } 2092315SN/A 2102315SN/A // 2112315SN/A // New accessors for new decoder. 2122315SN/A // 2132315SN/A uint64_t readIntReg(int reg_idx) 2142680SN/A { return actualTC->readIntReg(reg_idx); } 2152315SN/A 2162669SN/A FloatReg readFloatReg(int reg_idx) 2172680SN/A { return actualTC->readFloatReg(reg_idx); } 2182315SN/A 2192669SN/A FloatRegBits readFloatRegBits(int reg_idx) 2202680SN/A { return actualTC->readFloatRegBits(reg_idx); } 2212315SN/A 2229920Syasuko.eckert@amd.com CCReg readCCReg(int reg_idx) 2239920Syasuko.eckert@amd.com { return actualTC->readCCReg(reg_idx); } 2249920Syasuko.eckert@amd.com 2252315SN/A void setIntReg(int reg_idx, uint64_t val) 2262315SN/A { 2272680SN/A actualTC->setIntReg(reg_idx, val); 2282680SN/A checkerTC->setIntReg(reg_idx, val); 2292315SN/A } 2302315SN/A 2312669SN/A void setFloatReg(int reg_idx, FloatReg val) 2322315SN/A { 2332680SN/A actualTC->setFloatReg(reg_idx, val); 2342680SN/A checkerTC->setFloatReg(reg_idx, val); 2352315SN/A } 2362315SN/A 2372669SN/A void setFloatRegBits(int reg_idx, FloatRegBits val) 2382669SN/A { 2392680SN/A actualTC->setFloatRegBits(reg_idx, val); 2402680SN/A checkerTC->setFloatRegBits(reg_idx, val); 2412315SN/A } 2422315SN/A 2439920Syasuko.eckert@amd.com void setCCReg(int reg_idx, CCReg val) 2449920Syasuko.eckert@amd.com { 2459920Syasuko.eckert@amd.com actualTC->setCCReg(reg_idx, val); 2469920Syasuko.eckert@amd.com checkerTC->setCCReg(reg_idx, val); 2479920Syasuko.eckert@amd.com } 2489920Syasuko.eckert@amd.com 2498733Sgeoffrey.blake@arm.com /** Reads this thread's PC state. */ 2508733Sgeoffrey.blake@arm.com TheISA::PCState pcState() 2518733Sgeoffrey.blake@arm.com { return actualTC->pcState(); } 2522315SN/A 2538733Sgeoffrey.blake@arm.com /** Sets this thread's PC state. */ 2548733Sgeoffrey.blake@arm.com void pcState(const TheISA::PCState &val) 2552315SN/A { 2568733Sgeoffrey.blake@arm.com DPRINTF(Checker, "Changing PC to %s, old PC %s\n", 2578733Sgeoffrey.blake@arm.com val, checkerTC->pcState()); 2588733Sgeoffrey.blake@arm.com checkerTC->pcState(val); 2592315SN/A checkerCPU->recordPCChange(val); 2608733Sgeoffrey.blake@arm.com return actualTC->pcState(val); 2612315SN/A } 2622315SN/A 2638733Sgeoffrey.blake@arm.com void pcStateNoRecord(const TheISA::PCState &val) 2642315SN/A { 2658733Sgeoffrey.blake@arm.com return actualTC->pcState(val); 2662315SN/A } 2672315SN/A 2688733Sgeoffrey.blake@arm.com /** Reads this thread's PC. */ 2698733Sgeoffrey.blake@arm.com Addr instAddr() 2708733Sgeoffrey.blake@arm.com { return actualTC->instAddr(); } 2712669SN/A 2728733Sgeoffrey.blake@arm.com /** Reads this thread's next PC. */ 2738733Sgeoffrey.blake@arm.com Addr nextInstAddr() 2748733Sgeoffrey.blake@arm.com { return actualTC->nextInstAddr(); } 2758733Sgeoffrey.blake@arm.com 2768733Sgeoffrey.blake@arm.com /** Reads this thread's next PC. */ 2778733Sgeoffrey.blake@arm.com MicroPC microPC() 2788733Sgeoffrey.blake@arm.com { return actualTC->microPC(); } 2792669SN/A 2804172Ssaidi@eecs.umich.edu MiscReg readMiscRegNoEffect(int misc_reg) 2814172Ssaidi@eecs.umich.edu { return actualTC->readMiscRegNoEffect(misc_reg); } 2824172Ssaidi@eecs.umich.edu 2832315SN/A MiscReg readMiscReg(int misc_reg) 2842680SN/A { return actualTC->readMiscReg(misc_reg); } 2852315SN/A 2864172Ssaidi@eecs.umich.edu void setMiscRegNoEffect(int misc_reg, const MiscReg &val) 2874172Ssaidi@eecs.umich.edu { 2888733Sgeoffrey.blake@arm.com DPRINTF(Checker, "Setting misc reg with no effect: %d to both Checker" 2898733Sgeoffrey.blake@arm.com " and O3..\n", misc_reg); 2904172Ssaidi@eecs.umich.edu checkerTC->setMiscRegNoEffect(misc_reg, val); 2914172Ssaidi@eecs.umich.edu actualTC->setMiscRegNoEffect(misc_reg, val); 2924172Ssaidi@eecs.umich.edu } 2932315SN/A 2943468Sgblack@eecs.umich.edu void setMiscReg(int misc_reg, const MiscReg &val) 2952315SN/A { 2968733Sgeoffrey.blake@arm.com DPRINTF(Checker, "Setting misc reg with effect: %d to both Checker" 2978733Sgeoffrey.blake@arm.com " and O3..\n", misc_reg); 2982680SN/A checkerTC->setMiscReg(misc_reg, val); 2993468Sgblack@eecs.umich.edu actualTC->setMiscReg(misc_reg, val); 3002315SN/A } 3012315SN/A 3028733Sgeoffrey.blake@arm.com int flattenIntIndex(int reg) { return actualTC->flattenIntIndex(reg); } 3038733Sgeoffrey.blake@arm.com int flattenFloatIndex(int reg) { return actualTC->flattenFloatIndex(reg); } 3049920Syasuko.eckert@amd.com int flattenCCIndex(int reg) { return actualTC->flattenCCIndex(reg); } 30510033SAli.Saidi@ARM.com int flattenMiscIndex(int reg) { return actualTC->flattenMiscIndex(reg); } 3068733Sgeoffrey.blake@arm.com 3072315SN/A unsigned readStCondFailures() 3082680SN/A { return actualTC->readStCondFailures(); } 3092315SN/A 3102315SN/A void setStCondFailures(unsigned sc_failures) 3112315SN/A { 3122680SN/A actualTC->setStCondFailures(sc_failures); 3132315SN/A } 3142315SN/A 3152315SN/A // @todo: Fix this! 3162680SN/A bool misspeculating() { return actualTC->misspeculating(); } 3172315SN/A 3182680SN/A Counter readFuncExeInst() { return actualTC->readFuncExeInst(); } 3199426SAndreas.Sandberg@ARM.com 3209426SAndreas.Sandberg@ARM.com uint64_t readIntRegFlat(int idx) 3219426SAndreas.Sandberg@ARM.com { return actualTC->readIntRegFlat(idx); } 3229426SAndreas.Sandberg@ARM.com 3239426SAndreas.Sandberg@ARM.com void setIntRegFlat(int idx, uint64_t val) 3249426SAndreas.Sandberg@ARM.com { actualTC->setIntRegFlat(idx, val); } 3259426SAndreas.Sandberg@ARM.com 3269426SAndreas.Sandberg@ARM.com FloatReg readFloatRegFlat(int idx) 3279426SAndreas.Sandberg@ARM.com { return actualTC->readFloatRegFlat(idx); } 3289426SAndreas.Sandberg@ARM.com 3299426SAndreas.Sandberg@ARM.com void setFloatRegFlat(int idx, FloatReg val) 3309426SAndreas.Sandberg@ARM.com { actualTC->setFloatRegFlat(idx, val); } 3319426SAndreas.Sandberg@ARM.com 3329426SAndreas.Sandberg@ARM.com FloatRegBits readFloatRegBitsFlat(int idx) 3339426SAndreas.Sandberg@ARM.com { return actualTC->readFloatRegBitsFlat(idx); } 3349426SAndreas.Sandberg@ARM.com 3359426SAndreas.Sandberg@ARM.com void setFloatRegBitsFlat(int idx, FloatRegBits val) 3369426SAndreas.Sandberg@ARM.com { actualTC->setFloatRegBitsFlat(idx, val); } 3379920Syasuko.eckert@amd.com 3389920Syasuko.eckert@amd.com CCReg readCCRegFlat(int idx) 3399920Syasuko.eckert@amd.com { return actualTC->readCCRegFlat(idx); } 3409920Syasuko.eckert@amd.com 3419920Syasuko.eckert@amd.com void setCCRegFlat(int idx, CCReg val) 3429920Syasuko.eckert@amd.com { actualTC->setCCRegFlat(idx, val); } 3432315SN/A}; 3442315SN/A 3452315SN/A#endif // __CPU_CHECKER_EXEC_CONTEXT_HH__ 346