cpu.hh revision 12406
12315SN/A/* 212107SRekai.GonzalezAlberquilla@arm.com * Copyright (c) 2011, 2016 ARM Limited 39920Syasuko.eckert@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 48733Sgeoffrey.blake@arm.com * All rights reserved 58733Sgeoffrey.blake@arm.com * 68733Sgeoffrey.blake@arm.com * The license below extends only to copyright in the software and shall 78733Sgeoffrey.blake@arm.com * not be construed as granting a license to any other intellectual 88733Sgeoffrey.blake@arm.com * property including but not limited to intellectual property relating 98733Sgeoffrey.blake@arm.com * to a hardware implementation of the functionality of the software 108733Sgeoffrey.blake@arm.com * licensed hereunder. You may use the software subject to the license 118733Sgeoffrey.blake@arm.com * terms below provided that you ensure that this notice is replicated 128733Sgeoffrey.blake@arm.com * unmodified and in its entirety in all distributions of the software, 138733Sgeoffrey.blake@arm.com * modified or unmodified, in source code or in binary form. 148733Sgeoffrey.blake@arm.com * 152332SN/A * Copyright (c) 2006 The Regents of The University of Michigan 162315SN/A * All rights reserved. 172315SN/A * 182315SN/A * Redistribution and use in source and binary forms, with or without 192315SN/A * modification, are permitted provided that the following conditions are 202315SN/A * met: redistributions of source code must retain the above copyright 212315SN/A * notice, this list of conditions and the following disclaimer; 222315SN/A * redistributions in binary form must reproduce the above copyright 232315SN/A * notice, this list of conditions and the following disclaimer in the 242315SN/A * documentation and/or other materials provided with the distribution; 252315SN/A * neither the name of the copyright holders nor the names of its 262315SN/A * contributors may be used to endorse or promote products derived from 272315SN/A * this software without specific prior written permission. 282315SN/A * 292315SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302315SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312315SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322315SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332315SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342315SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352315SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362315SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372315SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382315SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392315SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402689Sktlim@umich.edu * 412689Sktlim@umich.edu * Authors: Kevin Lim 422315SN/A */ 432315SN/A 442315SN/A#ifndef __CPU_CHECKER_CPU_HH__ 452315SN/A#define __CPU_CHECKER_CPU_HH__ 462315SN/A 472315SN/A#include <list> 488229Snate@binkert.org#include <map> 492315SN/A#include <queue> 502315SN/A 512669Sktlim@umich.edu#include "arch/types.hh" 522315SN/A#include "base/statistics.hh" 532315SN/A#include "cpu/base.hh" 542315SN/A#include "cpu/base_dyn_inst.hh" 5510319SAndreas.Sandberg@ARM.com#include "cpu/exec_context.hh" 5612107SRekai.GonzalezAlberquilla@arm.com#include "cpu/inst_res.hh" 578229Snate@binkert.org#include "cpu/pc_event.hh" 582683Sktlim@umich.edu#include "cpu/simple_thread.hh" 592315SN/A#include "cpu/static_inst.hh" 608733Sgeoffrey.blake@arm.com#include "debug/Checker.hh" 6111608Snikos.nikoleris@arm.com#include "mem/request.hh" 628733Sgeoffrey.blake@arm.com#include "params/CheckerCPU.hh" 632315SN/A#include "sim/eventq.hh" 642315SN/A 6512406Sgabeblack@google.comclass BaseTLB; 662315SN/Atemplate <class> 672315SN/Aclass BaseDynInst; 682680Sktlim@umich.educlass ThreadContext; 692669Sktlim@umich.educlass Request; 702315SN/A 712350SN/A/** 722350SN/A * CheckerCPU class. Dynamically verifies instructions as they are 732350SN/A * completed by making sure that the instruction and its results match 742350SN/A * the independent execution of the benchmark inside the checker. The 752350SN/A * checker verifies instructions in order, regardless of the order in 762350SN/A * which instructions complete. There are certain results that can 772350SN/A * not be verified, specifically the result of a store conditional or 782350SN/A * the values of uncached accesses. In these cases, and with 792350SN/A * instructions marked as "IsUnverifiable", the checker assumes that 802350SN/A * the value from the main CPU's execution is correct and simply 812680Sktlim@umich.edu * copies that value. It provides a CheckerThreadContext (see 822683Sktlim@umich.edu * checker/thread_context.hh) that provides hooks for updating the 832680Sktlim@umich.edu * Checker's state through any ThreadContext accesses. This allows the 842350SN/A * checker to be able to correctly verify instructions, even with 852680Sktlim@umich.edu * external accesses to the ThreadContext that change state. 862350SN/A */ 8710319SAndreas.Sandberg@ARM.comclass CheckerCPU : public BaseCPU, public ExecContext 882315SN/A{ 892315SN/A protected: 902315SN/A typedef TheISA::MachInst MachInst; 912669Sktlim@umich.edu typedef TheISA::FloatReg FloatReg; 922669Sktlim@umich.edu typedef TheISA::FloatRegBits FloatRegBits; 932315SN/A typedef TheISA::MiscReg MiscReg; 9412109SRekai.GonzalezAlberquilla@arm.com using VecRegContainer = TheISA::VecRegContainer; 958832SAli.Saidi@ARM.com 968832SAli.Saidi@ARM.com /** id attached to all issued requests */ 978832SAli.Saidi@ARM.com MasterID masterId; 982315SN/A public: 9911169Sandreas.hansson@arm.com void init() override; 1002315SN/A 1015529Snate@binkert.org typedef CheckerCPUParams Params; 1022315SN/A CheckerCPU(Params *p); 1032315SN/A virtual ~CheckerCPU(); 1042315SN/A 1052315SN/A void setSystem(System *system); 1062315SN/A 1079608Sandreas.hansson@arm.com void setIcachePort(MasterPort *icache_port); 1082679Sktlim@umich.edu 1099608Sandreas.hansson@arm.com void setDcachePort(MasterPort *dcache_port); 1102679Sktlim@umich.edu 11111169Sandreas.hansson@arm.com MasterPort &getDataPort() override 1128887Sgeoffrey.blake@arm.com { 1139176Sandreas.hansson@arm.com // the checker does not have ports on its own so return the 1149176Sandreas.hansson@arm.com // data port of the actual CPU core 1159176Sandreas.hansson@arm.com assert(dcachePort); 1168887Sgeoffrey.blake@arm.com return *dcachePort; 1178887Sgeoffrey.blake@arm.com } 1188887Sgeoffrey.blake@arm.com 11911169Sandreas.hansson@arm.com MasterPort &getInstPort() override 1208887Sgeoffrey.blake@arm.com { 1219176Sandreas.hansson@arm.com // the checker does not have ports on its own so return the 1229176Sandreas.hansson@arm.com // data port of the actual CPU core 1239176Sandreas.hansson@arm.com assert(icachePort); 1248887Sgeoffrey.blake@arm.com return *icachePort; 1258887Sgeoffrey.blake@arm.com } 1262679Sktlim@umich.edu 1279176Sandreas.hansson@arm.com protected: 1289176Sandreas.hansson@arm.com 1299176Sandreas.hansson@arm.com std::vector<Process*> workload; 1309176Sandreas.hansson@arm.com 1319176Sandreas.hansson@arm.com System *systemPtr; 1329176Sandreas.hansson@arm.com 1339608Sandreas.hansson@arm.com MasterPort *icachePort; 1349608Sandreas.hansson@arm.com MasterPort *dcachePort; 1352315SN/A 1362680Sktlim@umich.edu ThreadContext *tc; 1372315SN/A 13812406Sgabeblack@google.com BaseTLB *itb; 13912406Sgabeblack@google.com BaseTLB *dtb; 1402315SN/A 1412315SN/A Addr dbg_vtophys(Addr addr); 1422315SN/A 1438733Sgeoffrey.blake@arm.com // ISAs like ARM can have multiple destination registers to check, 1448733Sgeoffrey.blake@arm.com // keep them all in a std::queue 14512107SRekai.GonzalezAlberquilla@arm.com std::queue<InstResult> result; 1462315SN/A 1472679Sktlim@umich.edu // Pointer to the one memory request. 1482679Sktlim@umich.edu RequestPtr memReq; 1492315SN/A 1502315SN/A StaticInstPtr curStaticInst; 1518733Sgeoffrey.blake@arm.com StaticInstPtr curMacroStaticInst; 1522315SN/A 1532315SN/A // number of simulated instructions 1542315SN/A Counter numInst; 1552315SN/A Counter startNumInst; 1562315SN/A 1572315SN/A std::queue<int> miscRegIdxs; 1582315SN/A 1599176Sandreas.hansson@arm.com public: 1609176Sandreas.hansson@arm.com 1619176Sandreas.hansson@arm.com // Primary thread being run. 1629176Sandreas.hansson@arm.com SimpleThread *thread; 1639176Sandreas.hansson@arm.com 16412406Sgabeblack@google.com BaseTLB* getITBPtr() { return itb; } 16512406Sgabeblack@google.com BaseTLB* getDTBPtr() { return dtb; } 1668733Sgeoffrey.blake@arm.com 16711169Sandreas.hansson@arm.com virtual Counter totalInsts() const override 1688887Sgeoffrey.blake@arm.com { 1698887Sgeoffrey.blake@arm.com return 0; 1708887Sgeoffrey.blake@arm.com } 1718887Sgeoffrey.blake@arm.com 17211169Sandreas.hansson@arm.com virtual Counter totalOps() const override 1732315SN/A { 1742930Sktlim@umich.edu return 0; 1752315SN/A } 1762315SN/A 1772315SN/A // number of simulated loads 1782315SN/A Counter numLoad; 1792315SN/A Counter startNumLoad; 1802315SN/A 18111168Sandreas.hansson@arm.com void serialize(CheckpointOut &cp) const override; 18211168Sandreas.hansson@arm.com void unserialize(CheckpointIn &cp) override; 1832315SN/A 1842315SN/A // These functions are only used in CPU models that split 1852315SN/A // effective address computation from the actual memory access. 18611169Sandreas.hansson@arm.com void setEA(Addr EA) override 18711169Sandreas.hansson@arm.com { panic("CheckerCPU::setEA() not implemented\n"); } 18811169Sandreas.hansson@arm.com Addr getEA() const override 18911169Sandreas.hansson@arm.com { panic("CheckerCPU::getEA() not implemented\n"); } 1902315SN/A 1912315SN/A // The register accessor methods provide the index of the 1922315SN/A // instruction's operand (e.g., 0 or 1), not the architectural 1932315SN/A // register index, to simplify the implementation of register 1942315SN/A // renaming. We find the architectural register index by indexing 1952315SN/A // into the instruction's own operand index table. Note that a 1962315SN/A // raw pointer to the StaticInst is provided instead of a 1972315SN/A // ref-counted StaticInstPtr to redice overhead. This is fine as 1982315SN/A // long as these methods don't copy the pointer into any long-term 1992315SN/A // storage (which is pretty hard to imagine they would have reason 2002315SN/A // to do). 2012315SN/A 20211169Sandreas.hansson@arm.com IntReg readIntRegOperand(const StaticInst *si, int idx) override 2032315SN/A { 20412106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->srcRegIdx(idx); 20512106SRekai.GonzalezAlberquilla@arm.com assert(reg.isIntReg()); 20612106SRekai.GonzalezAlberquilla@arm.com return thread->readIntReg(reg.index()); 2072315SN/A } 2082315SN/A 20911169Sandreas.hansson@arm.com FloatReg readFloatRegOperand(const StaticInst *si, int idx) override 2102315SN/A { 21112106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->srcRegIdx(idx); 21212106SRekai.GonzalezAlberquilla@arm.com assert(reg.isFloatReg()); 21312106SRekai.GonzalezAlberquilla@arm.com return thread->readFloatReg(reg.index()); 2142315SN/A } 2152315SN/A 21611169Sandreas.hansson@arm.com FloatRegBits readFloatRegOperandBits(const StaticInst *si, 21711169Sandreas.hansson@arm.com int idx) override 2182669Sktlim@umich.edu { 21912106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->srcRegIdx(idx); 22012106SRekai.GonzalezAlberquilla@arm.com assert(reg.isFloatReg()); 22112106SRekai.GonzalezAlberquilla@arm.com return thread->readFloatRegBits(reg.index()); 2222315SN/A } 2232315SN/A 22412109SRekai.GonzalezAlberquilla@arm.com /** 22512109SRekai.GonzalezAlberquilla@arm.com * Read source vector register operand. 22612109SRekai.GonzalezAlberquilla@arm.com */ 22712109SRekai.GonzalezAlberquilla@arm.com const VecRegContainer& readVecRegOperand(const StaticInst *si, 22812109SRekai.GonzalezAlberquilla@arm.com int idx) const override 22912109SRekai.GonzalezAlberquilla@arm.com { 23012109SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->srcRegIdx(idx); 23112109SRekai.GonzalezAlberquilla@arm.com assert(reg.isVecReg()); 23212109SRekai.GonzalezAlberquilla@arm.com return thread->readVecReg(reg); 23312109SRekai.GonzalezAlberquilla@arm.com } 23412109SRekai.GonzalezAlberquilla@arm.com 23512109SRekai.GonzalezAlberquilla@arm.com /** 23612109SRekai.GonzalezAlberquilla@arm.com * Read destination vector register operand for modification. 23712109SRekai.GonzalezAlberquilla@arm.com */ 23812109SRekai.GonzalezAlberquilla@arm.com VecRegContainer& getWritableVecRegOperand(const StaticInst *si, 23912109SRekai.GonzalezAlberquilla@arm.com int idx) override 24012109SRekai.GonzalezAlberquilla@arm.com { 24112109SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 24212109SRekai.GonzalezAlberquilla@arm.com assert(reg.isVecReg()); 24312109SRekai.GonzalezAlberquilla@arm.com return thread->getWritableVecReg(reg); 24412109SRekai.GonzalezAlberquilla@arm.com } 24512109SRekai.GonzalezAlberquilla@arm.com 24612109SRekai.GonzalezAlberquilla@arm.com /** Vector Register Lane Interfaces. */ 24712109SRekai.GonzalezAlberquilla@arm.com /** @{ */ 24812109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 8bit operand. */ 24912109SRekai.GonzalezAlberquilla@arm.com virtual ConstVecLane8 25012109SRekai.GonzalezAlberquilla@arm.com readVec8BitLaneOperand(const StaticInst *si, int idx) const 25112109SRekai.GonzalezAlberquilla@arm.com override 25212109SRekai.GonzalezAlberquilla@arm.com { 25312109SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 25412109SRekai.GonzalezAlberquilla@arm.com assert(reg.isVecReg()); 25512109SRekai.GonzalezAlberquilla@arm.com return thread->readVec8BitLaneReg(reg); 25612109SRekai.GonzalezAlberquilla@arm.com } 25712109SRekai.GonzalezAlberquilla@arm.com 25812109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 16bit operand. */ 25912109SRekai.GonzalezAlberquilla@arm.com virtual ConstVecLane16 26012109SRekai.GonzalezAlberquilla@arm.com readVec16BitLaneOperand(const StaticInst *si, int idx) const 26112109SRekai.GonzalezAlberquilla@arm.com override 26212109SRekai.GonzalezAlberquilla@arm.com { 26312109SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 26412109SRekai.GonzalezAlberquilla@arm.com assert(reg.isVecReg()); 26512109SRekai.GonzalezAlberquilla@arm.com return thread->readVec16BitLaneReg(reg); 26612109SRekai.GonzalezAlberquilla@arm.com } 26712109SRekai.GonzalezAlberquilla@arm.com 26812109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 32bit operand. */ 26912109SRekai.GonzalezAlberquilla@arm.com virtual ConstVecLane32 27012109SRekai.GonzalezAlberquilla@arm.com readVec32BitLaneOperand(const StaticInst *si, int idx) const 27112109SRekai.GonzalezAlberquilla@arm.com override 27212109SRekai.GonzalezAlberquilla@arm.com { 27312109SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 27412109SRekai.GonzalezAlberquilla@arm.com assert(reg.isVecReg()); 27512109SRekai.GonzalezAlberquilla@arm.com return thread->readVec32BitLaneReg(reg); 27612109SRekai.GonzalezAlberquilla@arm.com } 27712109SRekai.GonzalezAlberquilla@arm.com 27812109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 64bit operand. */ 27912109SRekai.GonzalezAlberquilla@arm.com virtual ConstVecLane64 28012109SRekai.GonzalezAlberquilla@arm.com readVec64BitLaneOperand(const StaticInst *si, int idx) const 28112109SRekai.GonzalezAlberquilla@arm.com override 28212109SRekai.GonzalezAlberquilla@arm.com { 28312109SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 28412109SRekai.GonzalezAlberquilla@arm.com assert(reg.isVecReg()); 28512109SRekai.GonzalezAlberquilla@arm.com return thread->readVec64BitLaneReg(reg); 28612109SRekai.GonzalezAlberquilla@arm.com } 28712109SRekai.GonzalezAlberquilla@arm.com 28812109SRekai.GonzalezAlberquilla@arm.com /** Write a lane of the destination vector operand. */ 28912109SRekai.GonzalezAlberquilla@arm.com template <typename LD> 29012109SRekai.GonzalezAlberquilla@arm.com void 29112109SRekai.GonzalezAlberquilla@arm.com setVecLaneOperandT(const StaticInst *si, int idx, const LD& val) 29212109SRekai.GonzalezAlberquilla@arm.com { 29312109SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 29412109SRekai.GonzalezAlberquilla@arm.com assert(reg.isVecReg()); 29512109SRekai.GonzalezAlberquilla@arm.com return thread->setVecLane(reg, val); 29612109SRekai.GonzalezAlberquilla@arm.com } 29712109SRekai.GonzalezAlberquilla@arm.com virtual void 29812109SRekai.GonzalezAlberquilla@arm.com setVecLaneOperand(const StaticInst *si, int idx, 29912109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::Byte>& val) override 30012109SRekai.GonzalezAlberquilla@arm.com { 30112109SRekai.GonzalezAlberquilla@arm.com setVecLaneOperandT(si, idx, val); 30212109SRekai.GonzalezAlberquilla@arm.com } 30312109SRekai.GonzalezAlberquilla@arm.com virtual void 30412109SRekai.GonzalezAlberquilla@arm.com setVecLaneOperand(const StaticInst *si, int idx, 30512109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::TwoByte>& val) override 30612109SRekai.GonzalezAlberquilla@arm.com { 30712109SRekai.GonzalezAlberquilla@arm.com setVecLaneOperandT(si, idx, val); 30812109SRekai.GonzalezAlberquilla@arm.com } 30912109SRekai.GonzalezAlberquilla@arm.com virtual void 31012109SRekai.GonzalezAlberquilla@arm.com setVecLaneOperand(const StaticInst *si, int idx, 31112109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::FourByte>& val) override 31212109SRekai.GonzalezAlberquilla@arm.com { 31312109SRekai.GonzalezAlberquilla@arm.com setVecLaneOperandT(si, idx, val); 31412109SRekai.GonzalezAlberquilla@arm.com } 31512109SRekai.GonzalezAlberquilla@arm.com virtual void 31612109SRekai.GonzalezAlberquilla@arm.com setVecLaneOperand(const StaticInst *si, int idx, 31712109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::EightByte>& val) override 31812109SRekai.GonzalezAlberquilla@arm.com { 31912109SRekai.GonzalezAlberquilla@arm.com setVecLaneOperandT(si, idx, val); 32012109SRekai.GonzalezAlberquilla@arm.com } 32112109SRekai.GonzalezAlberquilla@arm.com /** @} */ 32212109SRekai.GonzalezAlberquilla@arm.com 32312109SRekai.GonzalezAlberquilla@arm.com VecElem readVecElemOperand(const StaticInst *si, int idx) const override 32412109SRekai.GonzalezAlberquilla@arm.com { 32512109SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->srcRegIdx(idx); 32612109SRekai.GonzalezAlberquilla@arm.com return thread->readVecElem(reg); 32712109SRekai.GonzalezAlberquilla@arm.com } 32812109SRekai.GonzalezAlberquilla@arm.com 32911169Sandreas.hansson@arm.com CCReg readCCRegOperand(const StaticInst *si, int idx) override 3309920Syasuko.eckert@amd.com { 33112106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->srcRegIdx(idx); 33212106SRekai.GonzalezAlberquilla@arm.com assert(reg.isCCReg()); 33312106SRekai.GonzalezAlberquilla@arm.com return thread->readCCReg(reg.index()); 3349920Syasuko.eckert@amd.com } 3359920Syasuko.eckert@amd.com 33612107SRekai.GonzalezAlberquilla@arm.com template<typename T> 33712107SRekai.GonzalezAlberquilla@arm.com void setScalarResult(T&& t) 3388733Sgeoffrey.blake@arm.com { 33912107SRekai.GonzalezAlberquilla@arm.com result.push(InstResult(std::forward<T>(t), 34012107SRekai.GonzalezAlberquilla@arm.com InstResult::ResultType::Scalar)); 3418733Sgeoffrey.blake@arm.com } 3428733Sgeoffrey.blake@arm.com 34312109SRekai.GonzalezAlberquilla@arm.com template<typename T> 34412109SRekai.GonzalezAlberquilla@arm.com void setVecResult(T&& t) 34512109SRekai.GonzalezAlberquilla@arm.com { 34612109SRekai.GonzalezAlberquilla@arm.com result.push(InstResult(std::forward<T>(t), 34712109SRekai.GonzalezAlberquilla@arm.com InstResult::ResultType::VecReg)); 34812109SRekai.GonzalezAlberquilla@arm.com } 34912109SRekai.GonzalezAlberquilla@arm.com 35012109SRekai.GonzalezAlberquilla@arm.com template<typename T> 35112109SRekai.GonzalezAlberquilla@arm.com void setVecElemResult(T&& t) 35212109SRekai.GonzalezAlberquilla@arm.com { 35312109SRekai.GonzalezAlberquilla@arm.com result.push(InstResult(std::forward<T>(t), 35412109SRekai.GonzalezAlberquilla@arm.com InstResult::ResultType::VecElem)); 35512109SRekai.GonzalezAlberquilla@arm.com } 35612109SRekai.GonzalezAlberquilla@arm.com 35711169Sandreas.hansson@arm.com void setIntRegOperand(const StaticInst *si, int idx, 35811169Sandreas.hansson@arm.com IntReg val) override 3592315SN/A { 36012106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 36112106SRekai.GonzalezAlberquilla@arm.com assert(reg.isIntReg()); 36212106SRekai.GonzalezAlberquilla@arm.com thread->setIntReg(reg.index(), val); 36312107SRekai.GonzalezAlberquilla@arm.com setScalarResult(val); 3642315SN/A } 3652315SN/A 36611169Sandreas.hansson@arm.com void setFloatRegOperand(const StaticInst *si, int idx, 36711169Sandreas.hansson@arm.com FloatReg val) override 3682669Sktlim@umich.edu { 36912106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 37012106SRekai.GonzalezAlberquilla@arm.com assert(reg.isFloatReg()); 37112106SRekai.GonzalezAlberquilla@arm.com thread->setFloatReg(reg.index(), val); 37212107SRekai.GonzalezAlberquilla@arm.com setScalarResult(val); 3732315SN/A } 3742315SN/A 3753735Sstever@eecs.umich.edu void setFloatRegOperandBits(const StaticInst *si, int idx, 37611169Sandreas.hansson@arm.com FloatRegBits val) override 3772315SN/A { 37812106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 37912106SRekai.GonzalezAlberquilla@arm.com assert(reg.isFloatReg()); 38012106SRekai.GonzalezAlberquilla@arm.com thread->setFloatRegBits(reg.index(), val); 38112107SRekai.GonzalezAlberquilla@arm.com setScalarResult(val); 3822315SN/A } 3832315SN/A 38411169Sandreas.hansson@arm.com void setCCRegOperand(const StaticInst *si, int idx, CCReg val) override 3859920Syasuko.eckert@amd.com { 38612106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 38712106SRekai.GonzalezAlberquilla@arm.com assert(reg.isCCReg()); 38812106SRekai.GonzalezAlberquilla@arm.com thread->setCCReg(reg.index(), val); 38912107SRekai.GonzalezAlberquilla@arm.com setScalarResult((uint64_t)val); 3909920Syasuko.eckert@amd.com } 3919920Syasuko.eckert@amd.com 39212109SRekai.GonzalezAlberquilla@arm.com void setVecRegOperand(const StaticInst *si, int idx, 39312109SRekai.GonzalezAlberquilla@arm.com const VecRegContainer& val) override 39412109SRekai.GonzalezAlberquilla@arm.com { 39512109SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 39612109SRekai.GonzalezAlberquilla@arm.com assert(reg.isVecReg()); 39712109SRekai.GonzalezAlberquilla@arm.com thread->setVecReg(reg, val); 39812109SRekai.GonzalezAlberquilla@arm.com setVecResult(val); 39912109SRekai.GonzalezAlberquilla@arm.com } 40012109SRekai.GonzalezAlberquilla@arm.com 40112109SRekai.GonzalezAlberquilla@arm.com void setVecElemOperand(const StaticInst *si, int idx, 40212109SRekai.GonzalezAlberquilla@arm.com const VecElem val) override 40312109SRekai.GonzalezAlberquilla@arm.com { 40412109SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 40512109SRekai.GonzalezAlberquilla@arm.com assert(reg.isVecElem()); 40612109SRekai.GonzalezAlberquilla@arm.com thread->setVecElem(reg, val); 40712109SRekai.GonzalezAlberquilla@arm.com setVecElemResult(val); 40812109SRekai.GonzalezAlberquilla@arm.com } 40912109SRekai.GonzalezAlberquilla@arm.com 41011169Sandreas.hansson@arm.com bool readPredicate() override { return thread->readPredicate(); } 41111169Sandreas.hansson@arm.com void setPredicate(bool val) override 4128733Sgeoffrey.blake@arm.com { 4138733Sgeoffrey.blake@arm.com thread->setPredicate(val); 4148733Sgeoffrey.blake@arm.com } 4152669Sktlim@umich.edu 41611169Sandreas.hansson@arm.com TheISA::PCState pcState() const override { return thread->pcState(); } 41711169Sandreas.hansson@arm.com void pcState(const TheISA::PCState &val) override 4188733Sgeoffrey.blake@arm.com { 4198733Sgeoffrey.blake@arm.com DPRINTF(Checker, "Changing PC to %s, old PC %s.\n", 4208733Sgeoffrey.blake@arm.com val, thread->pcState()); 4218733Sgeoffrey.blake@arm.com thread->pcState(val); 4228733Sgeoffrey.blake@arm.com } 4238733Sgeoffrey.blake@arm.com Addr instAddr() { return thread->instAddr(); } 4248733Sgeoffrey.blake@arm.com Addr nextInstAddr() { return thread->nextInstAddr(); } 4258733Sgeoffrey.blake@arm.com MicroPC microPC() { return thread->microPC(); } 4268733Sgeoffrey.blake@arm.com ////////////////////////////////////////// 4272315SN/A 42810698Sandreas.hansson@arm.com MiscReg readMiscRegNoEffect(int misc_reg) const 4294172Ssaidi@eecs.umich.edu { 4304172Ssaidi@eecs.umich.edu return thread->readMiscRegNoEffect(misc_reg); 4314172Ssaidi@eecs.umich.edu } 4324172Ssaidi@eecs.umich.edu 43311169Sandreas.hansson@arm.com MiscReg readMiscReg(int misc_reg) override 4342315SN/A { 4352683Sktlim@umich.edu return thread->readMiscReg(misc_reg); 4362315SN/A } 4372315SN/A 4384172Ssaidi@eecs.umich.edu void setMiscRegNoEffect(int misc_reg, const MiscReg &val) 4392315SN/A { 44010034SGeoffrey.Blake@arm.com DPRINTF(Checker, "Setting misc reg %d with no effect to check later\n", misc_reg); 4414172Ssaidi@eecs.umich.edu miscRegIdxs.push(misc_reg); 4424172Ssaidi@eecs.umich.edu return thread->setMiscRegNoEffect(misc_reg, val); 4432315SN/A } 4442315SN/A 44511169Sandreas.hansson@arm.com void setMiscReg(int misc_reg, const MiscReg &val) override 4462315SN/A { 44710034SGeoffrey.Blake@arm.com DPRINTF(Checker, "Setting misc reg %d with effect to check later\n", misc_reg); 4482315SN/A miscRegIdxs.push(misc_reg); 4492683Sktlim@umich.edu return thread->setMiscReg(misc_reg, val); 4502315SN/A } 4512315SN/A 45211169Sandreas.hansson@arm.com MiscReg readMiscRegOperand(const StaticInst *si, int idx) override 4538733Sgeoffrey.blake@arm.com { 45412106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->srcRegIdx(idx); 45512106SRekai.GonzalezAlberquilla@arm.com assert(reg.isMiscReg()); 45612106SRekai.GonzalezAlberquilla@arm.com return thread->readMiscReg(reg.index()); 4578733Sgeoffrey.blake@arm.com } 4588733Sgeoffrey.blake@arm.com 45911169Sandreas.hansson@arm.com void setMiscRegOperand(const StaticInst *si, int idx, 46011169Sandreas.hansson@arm.com const MiscReg &val) override 4618733Sgeoffrey.blake@arm.com { 46212106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 46312106SRekai.GonzalezAlberquilla@arm.com assert(reg.isMiscReg()); 46412106SRekai.GonzalezAlberquilla@arm.com return this->setMiscReg(reg.index(), val); 4658733Sgeoffrey.blake@arm.com } 4668888Sgeoffrey.blake@arm.com 4678888Sgeoffrey.blake@arm.com#if THE_ISA == MIPS_ISA 46812106SRekai.GonzalezAlberquilla@arm.com MiscReg readRegOtherThread(const RegId& misc_reg, ThreadID tid) override 4698888Sgeoffrey.blake@arm.com { 4708888Sgeoffrey.blake@arm.com panic("MIPS MT not defined for CheckerCPU.\n"); 4718888Sgeoffrey.blake@arm.com return 0; 4728888Sgeoffrey.blake@arm.com } 4738888Sgeoffrey.blake@arm.com 47412106SRekai.GonzalezAlberquilla@arm.com void setRegOtherThread(const RegId& misc_reg, MiscReg val, 47512106SRekai.GonzalezAlberquilla@arm.com ThreadID tid) override 4768888Sgeoffrey.blake@arm.com { 4778888Sgeoffrey.blake@arm.com panic("MIPS MT not defined for CheckerCPU.\n"); 4788888Sgeoffrey.blake@arm.com } 4798888Sgeoffrey.blake@arm.com#endif 4808888Sgeoffrey.blake@arm.com 4818733Sgeoffrey.blake@arm.com ///////////////////////////////////////// 4828733Sgeoffrey.blake@arm.com 4838733Sgeoffrey.blake@arm.com void recordPCChange(const TheISA::PCState &val) 4848733Sgeoffrey.blake@arm.com { 4858733Sgeoffrey.blake@arm.com changedPC = true; 4868733Sgeoffrey.blake@arm.com newPCState = val; 4878733Sgeoffrey.blake@arm.com } 4882315SN/A 48911169Sandreas.hansson@arm.com void demapPage(Addr vaddr, uint64_t asn) override 4905358Sgblack@eecs.umich.edu { 4915358Sgblack@eecs.umich.edu this->itb->demapPage(vaddr, asn); 4925358Sgblack@eecs.umich.edu this->dtb->demapPage(vaddr, asn); 4935358Sgblack@eecs.umich.edu } 4945358Sgblack@eecs.umich.edu 49510529Smorr@cs.wisc.edu // monitor/mwait funtions 49611169Sandreas.hansson@arm.com void armMonitor(Addr address) override 49711169Sandreas.hansson@arm.com { BaseCPU::armMonitor(0, address); } 49811169Sandreas.hansson@arm.com bool mwait(PacketPtr pkt) override { return BaseCPU::mwait(0, pkt); } 49911169Sandreas.hansson@arm.com void mwaitAtomic(ThreadContext *tc) override 50011148Smitch.hayenga@arm.com { return BaseCPU::mwaitAtomic(0, tc, thread->dtb); } 50111169Sandreas.hansson@arm.com AddressMonitor *getAddrMonitor() override 50211169Sandreas.hansson@arm.com { return BaseCPU::getCpuAddrMonitor(0); } 50310529Smorr@cs.wisc.edu 5045358Sgblack@eecs.umich.edu void demapInstPage(Addr vaddr, uint64_t asn) 5055358Sgblack@eecs.umich.edu { 5065358Sgblack@eecs.umich.edu this->itb->demapPage(vaddr, asn); 5075358Sgblack@eecs.umich.edu } 5085358Sgblack@eecs.umich.edu 5095358Sgblack@eecs.umich.edu void demapDataPage(Addr vaddr, uint64_t asn) 5105358Sgblack@eecs.umich.edu { 5115358Sgblack@eecs.umich.edu this->dtb->demapPage(vaddr, asn); 5125358Sgblack@eecs.umich.edu } 5135358Sgblack@eecs.umich.edu 51411169Sandreas.hansson@arm.com Fault readMem(Addr addr, uint8_t *data, unsigned size, 51511608Snikos.nikoleris@arm.com Request::Flags flags) override; 51611608Snikos.nikoleris@arm.com Fault writeMem(uint8_t *data, unsigned size, Addr addr, 51711608Snikos.nikoleris@arm.com Request::Flags flags, uint64_t *res) override; 5188733Sgeoffrey.blake@arm.com 51911169Sandreas.hansson@arm.com unsigned int readStCondFailures() const override { 52010319SAndreas.Sandberg@ARM.com return thread->readStCondFailures(); 52110319SAndreas.Sandberg@ARM.com } 52210319SAndreas.Sandberg@ARM.com 52311169Sandreas.hansson@arm.com void setStCondFailures(unsigned int sc_failures) override 5248733Sgeoffrey.blake@arm.com {} 5258733Sgeoffrey.blake@arm.com ///////////////////////////////////////////////////// 5268733Sgeoffrey.blake@arm.com 52711169Sandreas.hansson@arm.com Fault hwrei() override { return thread->hwrei(); } 52811169Sandreas.hansson@arm.com bool simPalCheck(int palFunc) override 52911169Sandreas.hansson@arm.com { return thread->simPalCheck(palFunc); } 53011168Sandreas.hansson@arm.com void wakeup(ThreadID tid) override { } 5312315SN/A // Assume that the normal CPU's call to syscall was successful. 5322332SN/A // The checker's state would have already been updated by the syscall. 53311877Sbrandon.potter@amd.com void syscall(int64_t callnum, Fault *fault) override { } 5342315SN/A 5352315SN/A void handleError() 5362315SN/A { 5372315SN/A if (exitOnError) 5382732Sktlim@umich.edu dumpAndExit(); 5392315SN/A } 5402732Sktlim@umich.edu 5418733Sgeoffrey.blake@arm.com bool checkFlags(Request *unverified_req, Addr vAddr, 5428733Sgeoffrey.blake@arm.com Addr pAddr, int flags); 5432315SN/A 5442732Sktlim@umich.edu void dumpAndExit(); 5452732Sktlim@umich.edu 54611169Sandreas.hansson@arm.com ThreadContext *tcBase() override { return tc; } 5472683Sktlim@umich.edu SimpleThread *threadBase() { return thread; } 5482315SN/A 54912107SRekai.GonzalezAlberquilla@arm.com InstResult unverifiedResult; 5502669Sktlim@umich.edu Request *unverifiedReq; 5512679Sktlim@umich.edu uint8_t *unverifiedMemData; 5522315SN/A 5532315SN/A bool changedPC; 5542315SN/A bool willChangePC; 5558733Sgeoffrey.blake@arm.com TheISA::PCState newPCState; 5562315SN/A bool exitOnError; 5572354SN/A bool updateOnError; 5582732Sktlim@umich.edu bool warnOnlyOnLoadError; 5592315SN/A 5602315SN/A InstSeqNum youngestSN; 5612315SN/A}; 5622315SN/A 5632350SN/A/** 5642350SN/A * Templated Checker class. This Checker class is templated on the 5652350SN/A * DynInstPtr of the instruction type that will be verified. Proper 5662350SN/A * template instantiations of the Checker must be placed at the bottom 5672350SN/A * of checker/cpu.cc. 5682350SN/A */ 5698733Sgeoffrey.blake@arm.comtemplate <class Impl> 5702315SN/Aclass Checker : public CheckerCPU 5712315SN/A{ 5728733Sgeoffrey.blake@arm.com private: 5738733Sgeoffrey.blake@arm.com typedef typename Impl::DynInstPtr DynInstPtr; 5748733Sgeoffrey.blake@arm.com 5752315SN/A public: 5762315SN/A Checker(Params *p) 5779023Sgblack@eecs.umich.edu : CheckerCPU(p), updateThisCycle(false), unverifiedInst(NULL) 5782315SN/A { } 5792315SN/A 5802840Sktlim@umich.edu void switchOut(); 5812315SN/A void takeOverFrom(BaseCPU *oldCPU); 5822315SN/A 58310379Sandreas.hansson@arm.com void advancePC(const Fault &fault); 5848733Sgeoffrey.blake@arm.com 5852732Sktlim@umich.edu void verify(DynInstPtr &inst); 5862315SN/A 5872315SN/A void validateInst(DynInstPtr &inst); 5882315SN/A void validateExecution(DynInstPtr &inst); 5892315SN/A void validateState(); 5902315SN/A 59112107SRekai.GonzalezAlberquilla@arm.com void copyResult(DynInstPtr &inst, const InstResult& mismatch_val, 59212107SRekai.GonzalezAlberquilla@arm.com int start_idx); 5938733Sgeoffrey.blake@arm.com void handlePendingInt(); 5942732Sktlim@umich.edu 5952732Sktlim@umich.edu private: 5962732Sktlim@umich.edu void handleError(DynInstPtr &inst) 5972732Sktlim@umich.edu { 5982360SN/A if (exitOnError) { 5992732Sktlim@umich.edu dumpAndExit(inst); 6002360SN/A } else if (updateOnError) { 6012354SN/A updateThisCycle = true; 6022360SN/A } 6032732Sktlim@umich.edu } 6042732Sktlim@umich.edu 6052732Sktlim@umich.edu void dumpAndExit(DynInstPtr &inst); 6062732Sktlim@umich.edu 6072354SN/A bool updateThisCycle; 6082354SN/A 6092354SN/A DynInstPtr unverifiedInst; 6102354SN/A 6112315SN/A std::list<DynInstPtr> instList; 6122315SN/A typedef typename std::list<DynInstPtr>::iterator InstListIt; 6132315SN/A void dumpInsts(); 6142315SN/A}; 6152315SN/A 6162315SN/A#endif // __CPU_CHECKER_CPU_HH__ 617