base_dyn_inst_impl.hh revision 8229 
1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 */
42
43#include <iostream>
44#include <set>
45#include <sstream>
46#include <string>
47
48#include "base/cprintf.hh"
49#include "base/trace.hh"
50#include "config/the_isa.hh"
51#include "cpu/base_dyn_inst.hh"
52#include "cpu/exetrace.hh"
53#include "mem/request.hh"
54#include "sim/faults.hh"
55
56#define NOHASH
57#ifndef NOHASH
58
59#include "base/hashmap.hh"
60
61unsigned int MyHashFunc(const BaseDynInst *addr)
62{
63    unsigned a = (unsigned)addr;
64    unsigned hash = (((a >> 14) ^ ((a >> 2) & 0xffff))) & 0x7FFFFFFF;
65
66    return hash;
67}
68
69typedef m5::hash_map<const BaseDynInst *, const BaseDynInst *, MyHashFunc>
70my_hash_t;
71
72my_hash_t thishash;
73#endif
74
75template <class Impl>
76BaseDynInst<Impl>::BaseDynInst(StaticInstPtr _staticInst,
77                               TheISA::PCState _pc, TheISA::PCState _predPC,
78                               InstSeqNum seq_num, ImplCPU *cpu)
79  : staticInst(_staticInst), traceData(NULL), cpu(cpu)
80{
81    seqNum = seq_num;
82
83    pc = _pc;
84    predPC = _predPC;
85    predTaken = false;
86
87    initVars();
88}
89
90template <class Impl>
91BaseDynInst<Impl>::BaseDynInst(TheISA::ExtMachInst inst,
92                               TheISA::PCState _pc, TheISA::PCState _predPC,
93                               InstSeqNum seq_num, ImplCPU *cpu)
94  : staticInst(inst, _pc.instAddr()), traceData(NULL), cpu(cpu)
95{
96    seqNum = seq_num;
97
98    pc = _pc;
99    predPC = _predPC;
100    predTaken = false;
101
102    initVars();
103}
104
105template <class Impl>
106BaseDynInst<Impl>::BaseDynInst(StaticInstPtr &_staticInst)
107    : staticInst(_staticInst), traceData(NULL)
108{
109    seqNum = 0;
110    initVars();
111}
112
113template <class Impl>
114void
115BaseDynInst<Impl>::initVars()
116{
117    memData = NULL;
118    effAddr = 0;
119    effAddrValid = false;
120    physEffAddr = 0;
121
122    translationStarted = false;
123    translationCompleted = false;
124
125    isUncacheable = false;
126    reqMade = false;
127    readyRegs = 0;
128
129    instResult.integer = 0;
130    recordResult = true;
131
132    status.reset();
133
134    eaCalcDone = false;
135    memOpDone = false;
136    predicate = true;
137
138    lqIdx = -1;
139    sqIdx = -1;
140
141    // Eventually make this a parameter.
142    threadNumber = 0;
143
144    // Also make this a parameter, or perhaps get it from xc or cpu.
145    asid = 0;
146
147    // Initialize the fault to be NoFault.
148    fault = NoFault;
149
150#ifndef NDEBUG
151    ++cpu->instcount;
152
153    if (cpu->instcount > 1500) {
154#ifdef DEBUG
155        cpu->dumpInsts();
156        dumpSNList();
157#endif
158        assert(cpu->instcount <= 1500);
159    }
160
161    DPRINTF(DynInst,
162        "DynInst: [sn:%lli] Instruction created. Instcount for %s = %i\n",
163        seqNum, cpu->name(), cpu->instcount);
164#endif
165
166#ifdef DEBUG
167    cpu->snList.insert(seqNum);
168#endif
169}
170
171template <class Impl>
172BaseDynInst<Impl>::~BaseDynInst()
173{
174    if (memData) {
175        delete [] memData;
176    }
177
178    if (traceData) {
179        delete traceData;
180    }
181
182    fault = NoFault;
183
184#ifndef NDEBUG
185    --cpu->instcount;
186
187    DPRINTF(DynInst,
188        "DynInst: [sn:%lli] Instruction destroyed. Instcount for %s = %i\n",
189        seqNum, cpu->name(), cpu->instcount);
190#endif
191#ifdef DEBUG
192    cpu->snList.erase(seqNum);
193#endif
194}
195
196#ifdef DEBUG
197template <class Impl>
198void
199BaseDynInst<Impl>::dumpSNList()
200{
201    std::set<InstSeqNum>::iterator sn_it = cpu->snList.begin();
202
203    int count = 0;
204    while (sn_it != cpu->snList.end()) {
205        cprintf("%i: [sn:%lli] not destroyed\n", count, (*sn_it));
206        count++;
207        sn_it++;
208    }
209}
210#endif
211
212template <class Impl>
213void
214BaseDynInst<Impl>::dump()
215{
216    cprintf("T%d : %#08d `", threadNumber, pc.instAddr());
217    std::cout << staticInst->disassemble(pc.instAddr());
218    cprintf("'\n");
219}
220
221template <class Impl>
222void
223BaseDynInst<Impl>::dump(std::string &outstring)
224{
225    std::ostringstream s;
226    s << "T" << threadNumber << " : 0x" << pc.instAddr() << " "
227      << staticInst->disassemble(pc.instAddr());
228
229    outstring = s.str();
230}
231
232template <class Impl>
233void
234BaseDynInst<Impl>::markSrcRegReady()
235{
236    DPRINTF(IQ, "[sn:%lli] has %d ready out of %d sources. RTI %d)\n",
237            seqNum, readyRegs+1, numSrcRegs(), readyToIssue());
238    if (++readyRegs == numSrcRegs()) {
239        setCanIssue();
240    }
241}
242
243template <class Impl>
244void
245BaseDynInst<Impl>::markSrcRegReady(RegIndex src_idx)
246{
247    _readySrcRegIdx[src_idx] = true;
248
249    markSrcRegReady();
250}
251
252template <class Impl>
253bool
254BaseDynInst<Impl>::eaSrcsReady()
255{
256    // For now I am assuming that src registers 1..n-1 are the ones that the
257    // EA calc depends on.  (i.e. src reg 0 is the source of the data to be
258    // stored)
259
260    for (int i = 1; i < numSrcRegs(); ++i) {
261        if (!_readySrcRegIdx[i])
262            return false;
263    }
264
265    return true;
266}
267