base_dyn_inst_impl.hh revision 5737:f43dbc09fad3 
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#include <iostream>
32#include <set>
33#include <string>
34#include <sstream>
35
36#include "base/cprintf.hh"
37#include "base/trace.hh"
38
39#include "sim/faults.hh"
40#include "cpu/exetrace.hh"
41#include "mem/request.hh"
42
43#include "cpu/base_dyn_inst.hh"
44
45#define NOHASH
46#ifndef NOHASH
47
48#include "base/hashmap.hh"
49
50unsigned int MyHashFunc(const BaseDynInst *addr)
51{
52    unsigned a = (unsigned)addr;
53    unsigned hash = (((a >> 14) ^ ((a >> 2) & 0xffff))) & 0x7FFFFFFF;
54
55    return hash;
56}
57
58typedef m5::hash_map<const BaseDynInst *, const BaseDynInst *, MyHashFunc>
59my_hash_t;
60
61my_hash_t thishash;
62#endif
63
64template <class Impl>
65BaseDynInst<Impl>::BaseDynInst(StaticInstPtr _staticInst,
66                               Addr inst_PC, Addr inst_NPC,
67                               Addr inst_MicroPC,
68                               Addr pred_PC, Addr pred_NPC,
69                               Addr pred_MicroPC,
70                               InstSeqNum seq_num, ImplCPU *cpu)
71  : staticInst(_staticInst), traceData(NULL), cpu(cpu)
72{
73    seqNum = seq_num;
74
75    bool nextIsMicro =
76        staticInst->isMicroop() && !staticInst->isLastMicroop();
77
78    PC = inst_PC;
79    microPC = inst_MicroPC;
80    if (nextIsMicro) {
81        nextPC = inst_PC;
82        nextNPC = inst_NPC;
83        nextMicroPC = microPC + 1;
84    } else {
85        nextPC = inst_NPC;
86        nextNPC = nextPC + sizeof(TheISA::MachInst);
87        nextMicroPC = 0;
88    }
89    predPC = pred_PC;
90    predNPC = pred_NPC;
91    predMicroPC = pred_MicroPC;
92    predTaken = false;
93
94    initVars();
95}
96
97template <class Impl>
98BaseDynInst<Impl>::BaseDynInst(TheISA::ExtMachInst inst,
99                               Addr inst_PC, Addr inst_NPC,
100                               Addr inst_MicroPC,
101                               Addr pred_PC, Addr pred_NPC,
102                               Addr pred_MicroPC,
103                               InstSeqNum seq_num, ImplCPU *cpu)
104  : staticInst(inst, inst_PC), traceData(NULL), cpu(cpu)
105{
106    seqNum = seq_num;
107
108    bool nextIsMicro =
109        staticInst->isMicroop() && !staticInst->isLastMicroop();
110
111    PC = inst_PC;
112    microPC = inst_MicroPC;
113    if (nextIsMicro) {
114        nextPC = inst_PC;
115        nextNPC = inst_NPC;
116        nextMicroPC = microPC + 1;
117    } else {
118        nextPC = inst_NPC;
119        nextNPC = nextPC + sizeof(TheISA::MachInst);
120        nextMicroPC = 0;
121    }
122    predPC = pred_PC;
123    predNPC = pred_NPC;
124    predMicroPC = pred_MicroPC;
125    predTaken = false;
126
127    initVars();
128}
129
130template <class Impl>
131BaseDynInst<Impl>::BaseDynInst(StaticInstPtr &_staticInst)
132    : staticInst(_staticInst), traceData(NULL)
133{
134    seqNum = 0;
135    initVars();
136}
137
138template <class Impl>
139void
140BaseDynInst<Impl>::initVars()
141{
142    memData = NULL;
143    effAddr = 0;
144    effAddrValid = false;
145    physEffAddr = 0;
146
147    isUncacheable = false;
148    reqMade = false;
149    readyRegs = 0;
150
151    instResult.integer = 0;
152    recordResult = true;
153
154    status.reset();
155
156    eaCalcDone = false;
157    memOpDone = false;
158
159    lqIdx = -1;
160    sqIdx = -1;
161
162    // Eventually make this a parameter.
163    threadNumber = 0;
164
165    // Also make this a parameter, or perhaps get it from xc or cpu.
166    asid = 0;
167
168    // Initialize the fault to be NoFault.
169    fault = NoFault;
170
171#ifndef NDEBUG
172    ++cpu->instcount;
173
174    if (cpu->instcount > 1500) {
175#ifdef DEBUG
176        cpu->dumpInsts();
177        dumpSNList();
178#endif
179        assert(cpu->instcount <= 1500);
180    }
181
182    DPRINTF(DynInst,
183        "DynInst: [sn:%lli] Instruction created. Instcount for %s = %i\n",
184        seqNum, cpu->name(), cpu->instcount);
185#endif
186
187#ifdef DEBUG
188    cpu->snList.insert(seqNum);
189#endif
190}
191
192template <class Impl>
193BaseDynInst<Impl>::~BaseDynInst()
194{
195    if (memData) {
196        delete [] memData;
197    }
198
199    if (traceData) {
200        delete traceData;
201    }
202
203    fault = NoFault;
204
205#ifndef NDEBUG
206    --cpu->instcount;
207
208    DPRINTF(DynInst,
209        "DynInst: [sn:%lli] Instruction destroyed. Instcount for %s = %i\n",
210        seqNum, cpu->name(), cpu->instcount);
211#endif
212#ifdef DEBUG
213    cpu->snList.erase(seqNum);
214#endif
215}
216
217#ifdef DEBUG
218template <class Impl>
219void
220BaseDynInst<Impl>::dumpSNList()
221{
222    std::set<InstSeqNum>::iterator sn_it = cpu->snList.begin();
223
224    int count = 0;
225    while (sn_it != cpu->snList.end()) {
226        cprintf("%i: [sn:%lli] not destroyed\n", count, (*sn_it));
227        count++;
228        sn_it++;
229    }
230}
231#endif
232
233template <class Impl>
234void
235BaseDynInst<Impl>::prefetch(Addr addr, unsigned flags)
236{
237    // This is the "functional" implementation of prefetch.  Not much
238    // happens here since prefetches don't affect the architectural
239    // state.
240/*
241    // Generate a MemReq so we can translate the effective address.
242    MemReqPtr req = new MemReq(addr, thread->getXCProxy(), 1, flags);
243    req->asid = asid;
244
245    // Prefetches never cause faults.
246    fault = NoFault;
247
248    // note this is a local, not BaseDynInst::fault
249    Fault trans_fault = cpu->translateDataReadReq(req);
250
251    if (trans_fault == NoFault && !(req->isUncacheable())) {
252        // It's a valid address to cacheable space.  Record key MemReq
253        // parameters so we can generate another one just like it for
254        // the timing access without calling translate() again (which
255        // might mess up the TLB).
256        effAddr = req->vaddr;
257        physEffAddr = req->paddr;
258        memReqFlags = req->flags;
259    } else {
260        // Bogus address (invalid or uncacheable space).  Mark it by
261        // setting the eff_addr to InvalidAddr.
262        effAddr = physEffAddr = MemReq::inval_addr;
263    }
264
265    if (traceData) {
266        traceData->setAddr(addr);
267    }
268*/
269}
270
271template <class Impl>
272void
273BaseDynInst<Impl>::writeHint(Addr addr, int size, unsigned flags)
274{
275    // Not currently supported.
276}
277
278/**
279 * @todo Need to find a way to get the cache block size here.
280 */
281template <class Impl>
282Fault
283BaseDynInst<Impl>::copySrcTranslate(Addr src)
284{
285    // Not currently supported.
286    return NoFault;
287}
288
289/**
290 * @todo Need to find a way to get the cache block size here.
291 */
292template <class Impl>
293Fault
294BaseDynInst<Impl>::copy(Addr dest)
295{
296    // Not currently supported.
297    return NoFault;
298}
299
300template <class Impl>
301void
302BaseDynInst<Impl>::dump()
303{
304    cprintf("T%d : %#08d `", threadNumber, PC);
305    std::cout << staticInst->disassemble(PC);
306    cprintf("'\n");
307}
308
309template <class Impl>
310void
311BaseDynInst<Impl>::dump(std::string &outstring)
312{
313    std::ostringstream s;
314    s << "T" << threadNumber << " : 0x" << PC << " "
315      << staticInst->disassemble(PC);
316
317    outstring = s.str();
318}
319
320template <class Impl>
321void
322BaseDynInst<Impl>::markSrcRegReady()
323{
324    if (++readyRegs == numSrcRegs()) {
325        setCanIssue();
326    }
327}
328
329template <class Impl>
330void
331BaseDynInst<Impl>::markSrcRegReady(RegIndex src_idx)
332{
333    _readySrcRegIdx[src_idx] = true;
334
335    markSrcRegReady();
336}
337
338template <class Impl>
339bool
340BaseDynInst<Impl>::eaSrcsReady()
341{
342    // For now I am assuming that src registers 1..n-1 are the ones that the
343    // EA calc depends on.  (i.e. src reg 0 is the source of the data to be
344    // stored)
345
346    for (int i = 1; i < numSrcRegs(); ++i) {
347        if (!_readySrcRegIdx[i])
348            return false;
349    }
350
351    return true;
352}
353