base_dyn_inst_impl.hh revision 4572:5499df089a6c 
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#include <iostream>
32#include <set>
33#include <string>
34#include <sstream>
35
36#include "base/cprintf.hh"
37#include "base/trace.hh"
38
39#include "sim/faults.hh"
40#include "cpu/exetrace.hh"
41#include "mem/request.hh"
42
43#include "cpu/base_dyn_inst.hh"
44
45#define NOHASH
46#ifndef NOHASH
47
48#include "base/hashmap.hh"
49
50unsigned int MyHashFunc(const BaseDynInst *addr)
51{
52    unsigned a = (unsigned)addr;
53    unsigned hash = (((a >> 14) ^ ((a >> 2) & 0xffff))) & 0x7FFFFFFF;
54
55    return hash;
56}
57
58typedef m5::hash_map<const BaseDynInst *, const BaseDynInst *, MyHashFunc>
59my_hash_t;
60
61my_hash_t thishash;
62#endif
63
64template <class Impl>
65BaseDynInst<Impl>::BaseDynInst(TheISA::ExtMachInst machInst,
66                               Addr inst_PC, Addr inst_NPC,
67                               Addr pred_PC, Addr pred_NPC,
68                               InstSeqNum seq_num, ImplCPU *cpu)
69  : staticInst(machInst, inst_PC), traceData(NULL), cpu(cpu)
70{
71    seqNum = seq_num;
72
73    PC = inst_PC;
74    nextPC = inst_NPC;
75    nextNPC = nextPC + sizeof(TheISA::MachInst);
76    predPC = pred_PC;
77    predNPC = pred_NPC;
78    predTaken = false;
79
80    initVars();
81}
82
83template <class Impl>
84BaseDynInst<Impl>::BaseDynInst(StaticInstPtr &_staticInst)
85    : staticInst(_staticInst), traceData(NULL)
86{
87    seqNum = 0;
88    initVars();
89}
90
91template <class Impl>
92void
93BaseDynInst<Impl>::initVars()
94{
95    memData = NULL;
96    effAddr = 0;
97    effAddrValid = false;
98    physEffAddr = 0;
99
100    isUncacheable = false;
101    reqMade = false;
102    readyRegs = 0;
103
104    instResult.integer = 0;
105    recordResult = true;
106
107    status.reset();
108
109    eaCalcDone = false;
110    memOpDone = false;
111
112    lqIdx = -1;
113    sqIdx = -1;
114
115    // Eventually make this a parameter.
116    threadNumber = 0;
117
118    // Also make this a parameter, or perhaps get it from xc or cpu.
119    asid = 0;
120
121    // Initialize the fault to be NoFault.
122    fault = NoFault;
123
124    ++instcount;
125
126    if (instcount > 1500) {
127        cpu->dumpInsts();
128#ifdef DEBUG
129        dumpSNList();
130#endif
131        assert(instcount <= 1500);
132    }
133
134    DPRINTF(DynInst, "DynInst: [sn:%lli] Instruction created. Instcount=%i\n",
135            seqNum, instcount);
136
137#ifdef DEBUG
138    cpu->snList.insert(seqNum);
139#endif
140}
141
142template <class Impl>
143BaseDynInst<Impl>::~BaseDynInst()
144{
145    if (memData) {
146        delete [] memData;
147    }
148
149    if (traceData) {
150        delete traceData;
151    }
152
153    fault = NoFault;
154
155    --instcount;
156
157    DPRINTF(DynInst, "DynInst: [sn:%lli] Instruction destroyed. Instcount=%i\n",
158            seqNum, instcount);
159#ifdef DEBUG
160    cpu->snList.erase(seqNum);
161#endif
162}
163
164#ifdef DEBUG
165template <class Impl>
166void
167BaseDynInst<Impl>::dumpSNList()
168{
169    std::set<InstSeqNum>::iterator sn_it = cpu->snList.begin();
170
171    int count = 0;
172    while (sn_it != cpu->snList.end()) {
173        cprintf("%i: [sn:%lli] not destroyed\n", count, (*sn_it));
174        count++;
175        sn_it++;
176    }
177}
178#endif
179
180template <class Impl>
181void
182BaseDynInst<Impl>::prefetch(Addr addr, unsigned flags)
183{
184    // This is the "functional" implementation of prefetch.  Not much
185    // happens here since prefetches don't affect the architectural
186    // state.
187/*
188    // Generate a MemReq so we can translate the effective address.
189    MemReqPtr req = new MemReq(addr, thread->getXCProxy(), 1, flags);
190    req->asid = asid;
191
192    // Prefetches never cause faults.
193    fault = NoFault;
194
195    // note this is a local, not BaseDynInst::fault
196    Fault trans_fault = cpu->translateDataReadReq(req);
197
198    if (trans_fault == NoFault && !(req->isUncacheable())) {
199        // It's a valid address to cacheable space.  Record key MemReq
200        // parameters so we can generate another one just like it for
201        // the timing access without calling translate() again (which
202        // might mess up the TLB).
203        effAddr = req->vaddr;
204        physEffAddr = req->paddr;
205        memReqFlags = req->flags;
206    } else {
207        // Bogus address (invalid or uncacheable space).  Mark it by
208        // setting the eff_addr to InvalidAddr.
209        effAddr = physEffAddr = MemReq::inval_addr;
210    }
211
212    if (traceData) {
213        traceData->setAddr(addr);
214    }
215*/
216}
217
218template <class Impl>
219void
220BaseDynInst<Impl>::writeHint(Addr addr, int size, unsigned flags)
221{
222    // Not currently supported.
223}
224
225/**
226 * @todo Need to find a way to get the cache block size here.
227 */
228template <class Impl>
229Fault
230BaseDynInst<Impl>::copySrcTranslate(Addr src)
231{
232    // Not currently supported.
233    return NoFault;
234}
235
236/**
237 * @todo Need to find a way to get the cache block size here.
238 */
239template <class Impl>
240Fault
241BaseDynInst<Impl>::copy(Addr dest)
242{
243    // Not currently supported.
244    return NoFault;
245}
246
247template <class Impl>
248void
249BaseDynInst<Impl>::dump()
250{
251    cprintf("T%d : %#08d `", threadNumber, PC);
252    std::cout << staticInst->disassemble(PC);
253    cprintf("'\n");
254}
255
256template <class Impl>
257void
258BaseDynInst<Impl>::dump(std::string &outstring)
259{
260    std::ostringstream s;
261    s << "T" << threadNumber << " : 0x" << PC << " "
262      << staticInst->disassemble(PC);
263
264    outstring = s.str();
265}
266
267template <class Impl>
268void
269BaseDynInst<Impl>::markSrcRegReady()
270{
271    if (++readyRegs == numSrcRegs()) {
272        setCanIssue();
273    }
274}
275
276template <class Impl>
277void
278BaseDynInst<Impl>::markSrcRegReady(RegIndex src_idx)
279{
280    _readySrcRegIdx[src_idx] = true;
281
282    markSrcRegReady();
283}
284
285template <class Impl>
286bool
287BaseDynInst<Impl>::eaSrcsReady()
288{
289    // For now I am assuming that src registers 1..n-1 are the ones that the
290    // EA calc depends on.  (i.e. src reg 0 is the source of the data to be
291    // stored)
292
293    for (int i = 1; i < numSrcRegs(); ++i) {
294        if (!_readySrcRegIdx[i])
295            return false;
296    }
297
298    return true;
299}
300