base_dyn_inst_impl.hh revision 3801:5ea378e2bccd 
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#include <iostream>
32#include <set>
33#include <string>
34#include <sstream>
35
36#include "base/cprintf.hh"
37#include "base/trace.hh"
38
39#include "sim/faults.hh"
40#include "cpu/exetrace.hh"
41#include "mem/request.hh"
42
43#include "cpu/base_dyn_inst.hh"
44
45#define NOHASH
46#ifndef NOHASH
47
48#include "base/hashmap.hh"
49
50unsigned int MyHashFunc(const BaseDynInst *addr)
51{
52    unsigned a = (unsigned)addr;
53    unsigned hash = (((a >> 14) ^ ((a >> 2) & 0xffff))) & 0x7FFFFFFF;
54
55    return hash;
56}
57
58typedef m5::hash_map<const BaseDynInst *, const BaseDynInst *, MyHashFunc>
59my_hash_t;
60
61my_hash_t thishash;
62#endif
63
64template <class Impl>
65BaseDynInst<Impl>::BaseDynInst(TheISA::ExtMachInst machInst,
66                               Addr inst_PC, Addr inst_NPC,
67                               Addr pred_PC, Addr pred_NPC,
68                               InstSeqNum seq_num, ImplCPU *cpu)
69  : staticInst(machInst), traceData(NULL), cpu(cpu)
70{
71    seqNum = seq_num;
72
73    PC = inst_PC;
74    nextPC = inst_NPC;
75    nextNPC = nextPC + sizeof(TheISA::MachInst);
76    predPC = pred_PC;
77    predNPC = pred_NPC;
78    predTaken = false;
79
80    initVars();
81}
82
83template <class Impl>
84BaseDynInst<Impl>::BaseDynInst(StaticInstPtr &_staticInst)
85    : staticInst(_staticInst), traceData(NULL)
86{
87    seqNum = 0;
88    initVars();
89}
90
91template <class Impl>
92void
93BaseDynInst<Impl>::initVars()
94{
95    req = NULL;
96    memData = NULL;
97    effAddr = 0;
98    physEffAddr = 0;
99
100    readyRegs = 0;
101
102    instResult.integer = 0;
103    recordResult = true;
104
105    status.reset();
106
107    eaCalcDone = false;
108    memOpDone = false;
109
110    lqIdx = -1;
111    sqIdx = -1;
112
113    // Eventually make this a parameter.
114    threadNumber = 0;
115
116    // Also make this a parameter, or perhaps get it from xc or cpu.
117    asid = 0;
118
119    // Initialize the fault to be NoFault.
120    fault = NoFault;
121
122    ++instcount;
123
124    if (instcount > 1500) {
125        cpu->dumpInsts();
126#ifdef DEBUG
127        dumpSNList();
128#endif
129        assert(instcount <= 1500);
130    }
131
132    DPRINTF(DynInst, "DynInst: [sn:%lli] Instruction created. Instcount=%i\n",
133            seqNum, instcount);
134
135#ifdef DEBUG
136    cpu->snList.insert(seqNum);
137#endif
138}
139
140template <class Impl>
141BaseDynInst<Impl>::~BaseDynInst()
142{
143    if (req) {
144        delete req;
145    }
146
147    if (memData) {
148        delete [] memData;
149    }
150
151    if (traceData) {
152        delete traceData;
153    }
154
155    fault = NoFault;
156
157    --instcount;
158
159    DPRINTF(DynInst, "DynInst: [sn:%lli] Instruction destroyed. Instcount=%i\n",
160            seqNum, instcount);
161#ifdef DEBUG
162    cpu->snList.erase(seqNum);
163#endif
164}
165
166#ifdef DEBUG
167template <class Impl>
168void
169BaseDynInst<Impl>::dumpSNList()
170{
171    std::set<InstSeqNum>::iterator sn_it = cpu->snList.begin();
172
173    int count = 0;
174    while (sn_it != cpu->snList.end()) {
175        cprintf("%i: [sn:%lli] not destroyed\n", count, (*sn_it));
176        count++;
177        sn_it++;
178    }
179}
180#endif
181
182template <class Impl>
183void
184BaseDynInst<Impl>::prefetch(Addr addr, unsigned flags)
185{
186    // This is the "functional" implementation of prefetch.  Not much
187    // happens here since prefetches don't affect the architectural
188    // state.
189/*
190    // Generate a MemReq so we can translate the effective address.
191    MemReqPtr req = new MemReq(addr, thread->getXCProxy(), 1, flags);
192    req->asid = asid;
193
194    // Prefetches never cause faults.
195    fault = NoFault;
196
197    // note this is a local, not BaseDynInst::fault
198    Fault trans_fault = cpu->translateDataReadReq(req);
199
200    if (trans_fault == NoFault && !(req->isUncacheable())) {
201        // It's a valid address to cacheable space.  Record key MemReq
202        // parameters so we can generate another one just like it for
203        // the timing access without calling translate() again (which
204        // might mess up the TLB).
205        effAddr = req->vaddr;
206        physEffAddr = req->paddr;
207        memReqFlags = req->flags;
208    } else {
209        // Bogus address (invalid or uncacheable space).  Mark it by
210        // setting the eff_addr to InvalidAddr.
211        effAddr = physEffAddr = MemReq::inval_addr;
212    }
213
214    if (traceData) {
215        traceData->setAddr(addr);
216    }
217*/
218}
219
220template <class Impl>
221void
222BaseDynInst<Impl>::writeHint(Addr addr, int size, unsigned flags)
223{
224    // Not currently supported.
225}
226
227/**
228 * @todo Need to find a way to get the cache block size here.
229 */
230template <class Impl>
231Fault
232BaseDynInst<Impl>::copySrcTranslate(Addr src)
233{
234    // Not currently supported.
235    return NoFault;
236}
237
238/**
239 * @todo Need to find a way to get the cache block size here.
240 */
241template <class Impl>
242Fault
243BaseDynInst<Impl>::copy(Addr dest)
244{
245    // Not currently supported.
246    return NoFault;
247}
248
249template <class Impl>
250void
251BaseDynInst<Impl>::dump()
252{
253    cprintf("T%d : %#08d `", threadNumber, PC);
254    std::cout << staticInst->disassemble(PC);
255    cprintf("'\n");
256}
257
258template <class Impl>
259void
260BaseDynInst<Impl>::dump(std::string &outstring)
261{
262    std::ostringstream s;
263    s << "T" << threadNumber << " : 0x" << PC << " "
264      << staticInst->disassemble(PC);
265
266    outstring = s.str();
267}
268
269template <class Impl>
270void
271BaseDynInst<Impl>::markSrcRegReady()
272{
273    if (++readyRegs == numSrcRegs()) {
274        status.set(CanIssue);
275    }
276}
277
278template <class Impl>
279void
280BaseDynInst<Impl>::markSrcRegReady(RegIndex src_idx)
281{
282    _readySrcRegIdx[src_idx] = true;
283
284    markSrcRegReady();
285}
286
287template <class Impl>
288bool
289BaseDynInst<Impl>::eaSrcsReady()
290{
291    // For now I am assuming that src registers 1..n-1 are the ones that the
292    // EA calc depends on.  (i.e. src reg 0 is the source of the data to be
293    // stored)
294
295    for (int i = 1; i < numSrcRegs(); ++i) {
296        if (!_readySrcRegIdx[i])
297            return false;
298    }
299
300    return true;
301}
302