base_dyn_inst_impl.hh revision 13453:4a7a060ea26e
12810Srdreslin@umich.edu/* 211870Snikos.nikoleris@arm.com * Copyright (c) 2011 ARM Limited 39796Sprakash.ramrakhyani@arm.com * All rights reserved. 49796Sprakash.ramrakhyani@arm.com * 59796Sprakash.ramrakhyani@arm.com * The license below extends only to copyright in the software and shall 69796Sprakash.ramrakhyani@arm.com * not be construed as granting a license to any other intellectual 79796Sprakash.ramrakhyani@arm.com * property including but not limited to intellectual property relating 89796Sprakash.ramrakhyani@arm.com * to a hardware implementation of the functionality of the software 99796Sprakash.ramrakhyani@arm.com * licensed hereunder. You may use the software subject to the license 109796Sprakash.ramrakhyani@arm.com * terms below provided that you ensure that this notice is replicated 119796Sprakash.ramrakhyani@arm.com * unmodified and in its entirety in all distributions of the software, 129796Sprakash.ramrakhyani@arm.com * modified or unmodified, in source code or in binary form. 139796Sprakash.ramrakhyani@arm.com * 142810Srdreslin@umich.edu * Copyright (c) 2004-2006 The Regents of The University of Michigan 152810Srdreslin@umich.edu * All rights reserved. 162810Srdreslin@umich.edu * 172810Srdreslin@umich.edu * Redistribution and use in source and binary forms, with or without 182810Srdreslin@umich.edu * modification, are permitted provided that the following conditions are 192810Srdreslin@umich.edu * met: redistributions of source code must retain the above copyright 202810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer; 212810Srdreslin@umich.edu * redistributions in binary form must reproduce the above copyright 222810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer in the 232810Srdreslin@umich.edu * documentation and/or other materials provided with the distribution; 242810Srdreslin@umich.edu * neither the name of the copyright holders nor the names of its 252810Srdreslin@umich.edu * contributors may be used to endorse or promote products derived from 262810Srdreslin@umich.edu * this software without specific prior written permission. 272810Srdreslin@umich.edu * 282810Srdreslin@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292810Srdreslin@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302810Srdreslin@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312810Srdreslin@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322810Srdreslin@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332810Srdreslin@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342810Srdreslin@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352810Srdreslin@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362810Srdreslin@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372810Srdreslin@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382810Srdreslin@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392810Srdreslin@umich.edu * 402810Srdreslin@umich.edu * Authors: Kevin Lim 412810Srdreslin@umich.edu */ 422810Srdreslin@umich.edu 432810Srdreslin@umich.edu#ifndef __CPU_BASE_DYN_INST_IMPL_HH__ 442810Srdreslin@umich.edu#define __CPU_BASE_DYN_INST_IMPL_HH__ 452810Srdreslin@umich.edu 462810Srdreslin@umich.edu#include <iostream> 472810Srdreslin@umich.edu#include <set> 4811486Snikos.nikoleris@arm.com#include <sstream> 4911486Snikos.nikoleris@arm.com#include <string> 506216Snate@binkert.org 512810Srdreslin@umich.edu#include "base/cprintf.hh" 522810Srdreslin@umich.edu#include "base/trace.hh" 532810Srdreslin@umich.edu#include "config/the_isa.hh" 542814Srdreslin@umich.edu#include "cpu/base_dyn_inst.hh" 552810Srdreslin@umich.edu#include "cpu/exetrace.hh" 562810Srdreslin@umich.edu#include "debug/DynInst.hh" 572810Srdreslin@umich.edu#include "debug/IQ.hh" 589796Sprakash.ramrakhyani@arm.com#include "mem/request.hh" 5910360Sandreas.hansson@arm.com#include "sim/faults.hh" 602810Srdreslin@umich.edu 612810Srdreslin@umich.edutemplate <class Impl> 622810Srdreslin@umich.eduBaseDynInst<Impl>::BaseDynInst(const StaticInstPtr &_staticInst, 632810Srdreslin@umich.edu const StaticInstPtr &_macroop, 642810Srdreslin@umich.edu TheISA::PCState _pc, TheISA::PCState _predPC, 652810Srdreslin@umich.edu InstSeqNum seq_num, ImplCPU *cpu) 662810Srdreslin@umich.edu : staticInst(_staticInst), cpu(cpu), 672810Srdreslin@umich.edu thread(nullptr), 682810Srdreslin@umich.edu traceData(nullptr), 692810Srdreslin@umich.edu macroop(_macroop), 702810Srdreslin@umich.edu memData(nullptr), 7111189Sandreas.hansson@arm.com savedReq(nullptr), 722810Srdreslin@umich.edu savedSreqLow(nullptr), 732810Srdreslin@umich.edu savedSreqHigh(nullptr), 742810Srdreslin@umich.edu reqToVerify(nullptr) 752810Srdreslin@umich.edu{ 762810Srdreslin@umich.edu seqNum = seq_num; 776978SLisa.Hsu@amd.com 782810Srdreslin@umich.edu pc = _pc; 796978SLisa.Hsu@amd.com predPC = _predPC; 802810Srdreslin@umich.edu 816978SLisa.Hsu@amd.com initVars(); 822810Srdreslin@umich.edu} 8311484Snikos.nikoleris@arm.com 842810Srdreslin@umich.edutemplate <class Impl> 852810Srdreslin@umich.eduBaseDynInst<Impl>::BaseDynInst(const StaticInstPtr &_staticInst, 862810Srdreslin@umich.edu const StaticInstPtr &_macroop) 876978SLisa.Hsu@amd.com : staticInst(_staticInst), traceData(NULL), macroop(_macroop) 8811484Snikos.nikoleris@arm.com{ 892810Srdreslin@umich.edu seqNum = 0; 902810Srdreslin@umich.edu initVars(); 916227Snate@binkert.org} 926227Snate@binkert.org 932810Srdreslin@umich.edutemplate <class Impl> 946978SLisa.Hsu@amd.comvoid 952810Srdreslin@umich.eduBaseDynInst<Impl>::initVars() 962810Srdreslin@umich.edu{ 972810Srdreslin@umich.edu memData = NULL; 982810Srdreslin@umich.edu effAddr = 0; 992810Srdreslin@umich.edu physEffAddrLow = 0; 1002810Srdreslin@umich.edu physEffAddrHigh = 0; 1012810Srdreslin@umich.edu readyRegs = 0; 1022810Srdreslin@umich.edu memReqFlags = 0; 1032810Srdreslin@umich.edu 1042810Srdreslin@umich.edu status.reset(); 10510941Sdavid.guillen@arm.com 10610941Sdavid.guillen@arm.com instFlags.reset(); 1072810Srdreslin@umich.edu instFlags[RecordResult] = true; 1082810Srdreslin@umich.edu instFlags[Predicate] = true; 1096978SLisa.Hsu@amd.com 1102810Srdreslin@umich.edu lqIdx = -1; 1112810Srdreslin@umich.edu sqIdx = -1; 1122810Srdreslin@umich.edu 1139086Sandreas.hansson@arm.com // Eventually make this a parameter. 1149086Sandreas.hansson@arm.com threadNumber = 0; 1159086Sandreas.hansson@arm.com 1169086Sandreas.hansson@arm.com // Also make this a parameter, or perhaps get it from xc or cpu. 1179086Sandreas.hansson@arm.com asid = 0; 1189086Sandreas.hansson@arm.com 1199086Sandreas.hansson@arm.com // Initialize the fault to be NoFault. 1209086Sandreas.hansson@arm.com fault = NoFault; 1212810Srdreslin@umich.edu 1229796Sprakash.ramrakhyani@arm.com#ifndef NDEBUG 1232810Srdreslin@umich.edu ++cpu->instcount; 1242810Srdreslin@umich.edu 1259796Sprakash.ramrakhyani@arm.com if (cpu->instcount > 1500) { 1262810Srdreslin@umich.edu#ifdef DEBUG 1272810Srdreslin@umich.edu cpu->dumpInsts(); 1289796Sprakash.ramrakhyani@arm.com dumpSNList(); 1292810Srdreslin@umich.edu#endif 1302810Srdreslin@umich.edu assert(cpu->instcount <= 1500); 1312810Srdreslin@umich.edu } 1322810Srdreslin@umich.edu 1339796Sprakash.ramrakhyani@arm.com DPRINTF(DynInst, 1342810Srdreslin@umich.edu "DynInst: [sn:%lli] Instruction created. Instcount for %s = %i\n", 1352810Srdreslin@umich.edu seqNum, cpu->name(), cpu->instcount); 1362810Srdreslin@umich.edu#endif 1379796Sprakash.ramrakhyani@arm.com 1382810Srdreslin@umich.edu#ifdef DEBUG 1392810Srdreslin@umich.edu cpu->snList.insert(seqNum); 1402810Srdreslin@umich.edu#endif 1416227Snate@binkert.org 1422810Srdreslin@umich.edu} 1432810Srdreslin@umich.edu 1442810Srdreslin@umich.edutemplate <class Impl> 1452810Srdreslin@umich.eduBaseDynInst<Impl>::~BaseDynInst() 1462810Srdreslin@umich.edu{ 1472810Srdreslin@umich.edu if (memData) { 1482810Srdreslin@umich.edu delete [] memData; 1492810Srdreslin@umich.edu } 1502810Srdreslin@umich.edu 1512810Srdreslin@umich.edu if (traceData) { 1522810Srdreslin@umich.edu delete traceData; 1532810Srdreslin@umich.edu } 1542810Srdreslin@umich.edu 1552810Srdreslin@umich.edu fault = NoFault; 1562810Srdreslin@umich.edu 1572810Srdreslin@umich.edu#ifndef NDEBUG 1582810Srdreslin@umich.edu --cpu->instcount; 1592810Srdreslin@umich.edu 1602810Srdreslin@umich.edu DPRINTF(DynInst, 1612810Srdreslin@umich.edu "DynInst: [sn:%lli] Instruction destroyed. Instcount for %s = %i\n", 1622810Srdreslin@umich.edu seqNum, cpu->name(), cpu->instcount); 16311484Snikos.nikoleris@arm.com#endif 1642810Srdreslin@umich.edu#ifdef DEBUG 1652810Srdreslin@umich.edu cpu->snList.erase(seqNum); 1662810Srdreslin@umich.edu#endif 16710815Sdavid.guillen@arm.com 1682810Srdreslin@umich.edu} 1699214Slena@cs.wisc.edu 1709214Slena@cs.wisc.edu#ifdef DEBUG 1712810Srdreslin@umich.edutemplate <class Impl> 1722810Srdreslin@umich.eduvoid 17310815Sdavid.guillen@arm.comBaseDynInst<Impl>::dumpSNList() 17411870Snikos.nikoleris@arm.com{ 17510815Sdavid.guillen@arm.com std::set<InstSeqNum>::iterator sn_it = cpu->snList.begin(); 17611870Snikos.nikoleris@arm.com 17710815Sdavid.guillen@arm.com int count = 0; 17810815Sdavid.guillen@arm.com while (sn_it != cpu->snList.end()) { 17910815Sdavid.guillen@arm.com cprintf("%i: [sn:%lli] not destroyed\n", count, (*sn_it)); 18011870Snikos.nikoleris@arm.com count++; 1812810Srdreslin@umich.edu sn_it++; 1822810Srdreslin@umich.edu } 1832810Srdreslin@umich.edu} 1842810Srdreslin@umich.edu#endif 1852810Srdreslin@umich.edu 1862810Srdreslin@umich.edutemplate <class Impl> 1872810Srdreslin@umich.eduvoid 18811722Ssophiane.senni@gmail.comBaseDynInst<Impl>::dump() 18911722Ssophiane.senni@gmail.com{ 19011722Ssophiane.senni@gmail.com cprintf("T%d : %#08d `", threadNumber, pc.instAddr()); 19111722Ssophiane.senni@gmail.com std::cout << staticInst->disassemble(pc.instAddr()); 19211722Ssophiane.senni@gmail.com cprintf("'\n"); 19311722Ssophiane.senni@gmail.com} 19411722Ssophiane.senni@gmail.com 19511722Ssophiane.senni@gmail.comtemplate <class Impl> 19611722Ssophiane.senni@gmail.comvoid 19711722Ssophiane.senni@gmail.comBaseDynInst<Impl>::dump(std::string &outstring) 1982810Srdreslin@umich.edu{ 1992810Srdreslin@umich.edu std::ostringstream s; 2006227Snate@binkert.org s << "T" << threadNumber << " : 0x" << pc.instAddr() << " " 2012810Srdreslin@umich.edu << staticInst->disassemble(pc.instAddr()); 2022810Srdreslin@umich.edu 2032810Srdreslin@umich.edu outstring = s.str(); 2042810Srdreslin@umich.edu} 2052810Srdreslin@umich.edu 2062810Srdreslin@umich.edutemplate <class Impl> 2072810Srdreslin@umich.eduvoid 2082810Srdreslin@umich.eduBaseDynInst<Impl>::markSrcRegReady() 2092810Srdreslin@umich.edu{ 2102810Srdreslin@umich.edu DPRINTF(IQ, "[sn:%lli] has %d ready out of %d sources. RTI %d)\n", 2112810Srdreslin@umich.edu seqNum, readyRegs+1, numSrcRegs(), readyToIssue()); 21211722Ssophiane.senni@gmail.com if (++readyRegs == numSrcRegs()) { 21311722Ssophiane.senni@gmail.com setCanIssue(); 21411484Snikos.nikoleris@arm.com } 2156227Snate@binkert.org} 2162810Srdreslin@umich.edu 2172810Srdreslin@umich.edutemplate <class Impl> 2182810Srdreslin@umich.eduvoid 2192810Srdreslin@umich.eduBaseDynInst<Impl>::markSrcRegReady(RegIndex src_idx) 2202810Srdreslin@umich.edu{ 2212810Srdreslin@umich.edu _readySrcRegIdx[src_idx] = true; 2222810Srdreslin@umich.edu 2232810Srdreslin@umich.edu markSrcRegReady(); 2242810Srdreslin@umich.edu} 2252810Srdreslin@umich.edu 2262810Srdreslin@umich.edutemplate <class Impl> 2272810Srdreslin@umich.edubool 22810815Sdavid.guillen@arm.comBaseDynInst<Impl>::eaSrcsReady() const 22910028SGiacomo.Gabrielli@arm.com{ 2302810Srdreslin@umich.edu // For now I am assuming that src registers 1..n-1 are the ones that the 2312810Srdreslin@umich.edu // EA calc depends on. (i.e. src reg 0 is the source of the data to be 2322810Srdreslin@umich.edu // stored) 2332810Srdreslin@umich.edu 2342810Srdreslin@umich.edu for (int i = 1; i < numSrcRegs(); ++i) { 2352810Srdreslin@umich.edu if (!_readySrcRegIdx[i]) 2362810Srdreslin@umich.edu return false; 23711484Snikos.nikoleris@arm.com } 2382810Srdreslin@umich.edu 2392810Srdreslin@umich.edu return true; 2402810Srdreslin@umich.edu} 2412810Srdreslin@umich.edu 24210815Sdavid.guillen@arm.com#endif//__CPU_BASE_DYN_INST_IMPL_HH__ 24310941Sdavid.guillen@arm.com