base_dyn_inst_impl.hh revision 11097:da477ae38907 
1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 */
42
43#ifndef __CPU_BASE_DYN_INST_IMPL_HH__
44#define __CPU_BASE_DYN_INST_IMPL_HH__
45
46#include <iostream>
47#include <set>
48#include <sstream>
49#include <string>
50
51#include "base/cprintf.hh"
52#include "base/trace.hh"
53#include "config/the_isa.hh"
54#include "cpu/base_dyn_inst.hh"
55#include "cpu/exetrace.hh"
56#include "debug/DynInst.hh"
57#include "debug/IQ.hh"
58#include "mem/request.hh"
59#include "sim/faults.hh"
60
61template <class Impl>
62BaseDynInst<Impl>::BaseDynInst(const StaticInstPtr &_staticInst,
63                               const StaticInstPtr &_macroop,
64                               TheISA::PCState _pc, TheISA::PCState _predPC,
65                               InstSeqNum seq_num, ImplCPU *cpu)
66  : staticInst(_staticInst), cpu(cpu), traceData(NULL), macroop(_macroop)
67{
68    seqNum = seq_num;
69
70    pc = _pc;
71    predPC = _predPC;
72
73    initVars();
74}
75
76template <class Impl>
77BaseDynInst<Impl>::BaseDynInst(const StaticInstPtr &_staticInst,
78                               const StaticInstPtr &_macroop)
79    : staticInst(_staticInst), traceData(NULL), macroop(_macroop)
80{
81    seqNum = 0;
82    initVars();
83}
84
85template <class Impl>
86void
87BaseDynInst<Impl>::initVars()
88{
89    memData = NULL;
90    effAddr = 0;
91    physEffAddrLow = 0;
92    physEffAddrHigh = 0;
93    readyRegs = 0;
94    memReqFlags = 0;
95
96    status.reset();
97
98    instFlags.reset();
99    instFlags[RecordResult] = true;
100    instFlags[Predicate] = true;
101
102    lqIdx = -1;
103    sqIdx = -1;
104
105    // Eventually make this a parameter.
106    threadNumber = 0;
107
108    // Also make this a parameter, or perhaps get it from xc or cpu.
109    asid = 0;
110
111    // Initialize the fault to be NoFault.
112    fault = NoFault;
113
114#ifndef NDEBUG
115    ++cpu->instcount;
116
117    if (cpu->instcount > 1500) {
118#ifdef DEBUG
119        cpu->dumpInsts();
120        dumpSNList();
121#endif
122        assert(cpu->instcount <= 1500);
123    }
124
125    DPRINTF(DynInst,
126        "DynInst: [sn:%lli] Instruction created. Instcount for %s = %i\n",
127        seqNum, cpu->name(), cpu->instcount);
128#endif
129
130#ifdef DEBUG
131    cpu->snList.insert(seqNum);
132#endif
133
134    reqToVerify = NULL;
135}
136
137template <class Impl>
138BaseDynInst<Impl>::~BaseDynInst()
139{
140    if (memData) {
141        delete [] memData;
142    }
143
144    if (traceData) {
145        delete traceData;
146    }
147
148    fault = NoFault;
149
150#ifndef NDEBUG
151    --cpu->instcount;
152
153    DPRINTF(DynInst,
154        "DynInst: [sn:%lli] Instruction destroyed. Instcount for %s = %i\n",
155        seqNum, cpu->name(), cpu->instcount);
156#endif
157#ifdef DEBUG
158    cpu->snList.erase(seqNum);
159#endif
160
161    if (reqToVerify)
162        delete reqToVerify;
163}
164
165#ifdef DEBUG
166template <class Impl>
167void
168BaseDynInst<Impl>::dumpSNList()
169{
170    std::set<InstSeqNum>::iterator sn_it = cpu->snList.begin();
171
172    int count = 0;
173    while (sn_it != cpu->snList.end()) {
174        cprintf("%i: [sn:%lli] not destroyed\n", count, (*sn_it));
175        count++;
176        sn_it++;
177    }
178}
179#endif
180
181template <class Impl>
182void
183BaseDynInst<Impl>::dump()
184{
185    cprintf("T%d : %#08d `", threadNumber, pc.instAddr());
186    std::cout << staticInst->disassemble(pc.instAddr());
187    cprintf("'\n");
188}
189
190template <class Impl>
191void
192BaseDynInst<Impl>::dump(std::string &outstring)
193{
194    std::ostringstream s;
195    s << "T" << threadNumber << " : 0x" << pc.instAddr() << " "
196      << staticInst->disassemble(pc.instAddr());
197
198    outstring = s.str();
199}
200
201template <class Impl>
202void
203BaseDynInst<Impl>::markSrcRegReady()
204{
205    DPRINTF(IQ, "[sn:%lli] has %d ready out of %d sources. RTI %d)\n",
206            seqNum, readyRegs+1, numSrcRegs(), readyToIssue());
207    if (++readyRegs == numSrcRegs()) {
208        setCanIssue();
209    }
210}
211
212template <class Impl>
213void
214BaseDynInst<Impl>::markSrcRegReady(RegIndex src_idx)
215{
216    _readySrcRegIdx[src_idx] = true;
217
218    markSrcRegReady();
219}
220
221template <class Impl>
222bool
223BaseDynInst<Impl>::eaSrcsReady()
224{
225    // For now I am assuming that src registers 1..n-1 are the ones that the
226    // EA calc depends on.  (i.e. src reg 0 is the source of the data to be
227    // stored)
228
229    for (int i = 1; i < numSrcRegs(); ++i) {
230        if (!_readySrcRegIdx[i])
231            return false;
232    }
233
234    return true;
235}
236
237#endif//__CPU_BASE_DYN_INST_IMPL_HH__
238