base_dyn_inst_impl.hh revision 4032
11060SN/A/* 22702SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31060SN/A * All rights reserved. 41060SN/A * 51060SN/A * Redistribution and use in source and binary forms, with or without 61060SN/A * modification, are permitted provided that the following conditions are 71060SN/A * met: redistributions of source code must retain the above copyright 81060SN/A * notice, this list of conditions and the following disclaimer; 91060SN/A * redistributions in binary form must reproduce the above copyright 101060SN/A * notice, this list of conditions and the following disclaimer in the 111060SN/A * documentation and/or other materials provided with the distribution; 121060SN/A * neither the name of the copyright holders nor the names of its 131060SN/A * contributors may be used to endorse or promote products derived from 141060SN/A * this software without specific prior written permission. 151060SN/A * 161060SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171060SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181060SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191060SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201060SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211060SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221060SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231060SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241060SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251060SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261060SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A * 282665SN/A * Authors: Kevin Lim 291060SN/A */ 301060SN/A 311060SN/A#include <iostream> 322292SN/A#include <set> 331060SN/A#include <string> 341060SN/A#include <sstream> 351060SN/A 361060SN/A#include "base/cprintf.hh" 371061SN/A#include "base/trace.hh" 381060SN/A 392980Sgblack@eecs.umich.edu#include "sim/faults.hh" 401060SN/A#include "cpu/exetrace.hh" 412669SN/A#include "mem/request.hh" 421060SN/A 431060SN/A#include "cpu/base_dyn_inst.hh" 441060SN/A 451060SN/A#define NOHASH 461060SN/A#ifndef NOHASH 471060SN/A 481060SN/A#include "base/hashmap.hh" 491060SN/A 501060SN/Aunsigned int MyHashFunc(const BaseDynInst *addr) 511060SN/A{ 522292SN/A unsigned a = (unsigned)addr; 532292SN/A unsigned hash = (((a >> 14) ^ ((a >> 2) & 0xffff))) & 0x7FFFFFFF; 541060SN/A 552292SN/A return hash; 561060SN/A} 571060SN/A 582292SN/Atypedef m5::hash_map<const BaseDynInst *, const BaseDynInst *, MyHashFunc> 592292SN/Amy_hash_t; 602292SN/A 611060SN/Amy_hash_t thishash; 621060SN/A#endif 631060SN/A 641061SN/Atemplate <class Impl> 653801Sgblack@eecs.umich.eduBaseDynInst<Impl>::BaseDynInst(TheISA::ExtMachInst machInst, 663801Sgblack@eecs.umich.edu Addr inst_PC, Addr inst_NPC, 673794Sgblack@eecs.umich.edu Addr pred_PC, Addr pred_NPC, 683794Sgblack@eecs.umich.edu InstSeqNum seq_num, ImplCPU *cpu) 692733SN/A : staticInst(machInst), traceData(NULL), cpu(cpu) 701060SN/A{ 711464SN/A seqNum = seq_num; 721061SN/A 731464SN/A PC = inst_PC; 743801Sgblack@eecs.umich.edu nextPC = inst_NPC; 752980Sgblack@eecs.umich.edu nextNPC = nextPC + sizeof(TheISA::MachInst); 761464SN/A predPC = pred_PC; 773794Sgblack@eecs.umich.edu predNPC = pred_NPC; 783794Sgblack@eecs.umich.edu predTaken = false; 791464SN/A 801464SN/A initVars(); 811464SN/A} 821464SN/A 831464SN/Atemplate <class Impl> 842107SN/ABaseDynInst<Impl>::BaseDynInst(StaticInstPtr &_staticInst) 851464SN/A : staticInst(_staticInst), traceData(NULL) 861464SN/A{ 872292SN/A seqNum = 0; 881464SN/A initVars(); 891464SN/A} 901464SN/A 911464SN/Atemplate <class Impl> 921464SN/Avoid 931464SN/ABaseDynInst<Impl>::initVars() 941464SN/A{ 952678SN/A memData = NULL; 962669SN/A effAddr = 0; 974032Sktlim@umich.edu effAddrValid = false; 982669SN/A physEffAddr = 0; 991060SN/A 1004032Sktlim@umich.edu isUncacheable = false; 1014032Sktlim@umich.edu reqMade = false; 1021060SN/A readyRegs = 0; 1031060SN/A 1042702SN/A instResult.integer = 0; 1053326Sktlim@umich.edu recordResult = true; 1062702SN/A 1072731SN/A status.reset(); 1082731SN/A 1091464SN/A eaCalcDone = false; 1102292SN/A memOpDone = false; 1112731SN/A 1122292SN/A lqIdx = -1; 1132292SN/A sqIdx = -1; 1142292SN/A 1151060SN/A // Eventually make this a parameter. 1161060SN/A threadNumber = 0; 1171464SN/A 1181060SN/A // Also make this a parameter, or perhaps get it from xc or cpu. 1191060SN/A asid = 0; 1201060SN/A 1212698SN/A // Initialize the fault to be NoFault. 1222292SN/A fault = NoFault; 1231060SN/A 1241060SN/A ++instcount; 1251060SN/A 1262292SN/A if (instcount > 1500) { 1272292SN/A cpu->dumpInsts(); 1282292SN/A#ifdef DEBUG 1292292SN/A dumpSNList(); 1302292SN/A#endif 1312292SN/A assert(instcount <= 1500); 1322292SN/A } 1332292SN/A 1342292SN/A DPRINTF(DynInst, "DynInst: [sn:%lli] Instruction created. Instcount=%i\n", 1352292SN/A seqNum, instcount); 1362292SN/A 1372292SN/A#ifdef DEBUG 1382292SN/A cpu->snList.insert(seqNum); 1392292SN/A#endif 1401060SN/A} 1411060SN/A 1421061SN/Atemplate <class Impl> 1431060SN/ABaseDynInst<Impl>::~BaseDynInst() 1441060SN/A{ 1452678SN/A if (memData) { 1462678SN/A delete [] memData; 1472292SN/A } 1482292SN/A 1492292SN/A if (traceData) { 1502292SN/A delete traceData; 1512292SN/A } 1522292SN/A 1532348SN/A fault = NoFault; 1542348SN/A 1551060SN/A --instcount; 1562292SN/A 1572292SN/A DPRINTF(DynInst, "DynInst: [sn:%lli] Instruction destroyed. Instcount=%i\n", 1582292SN/A seqNum, instcount); 1592292SN/A#ifdef DEBUG 1602292SN/A cpu->snList.erase(seqNum); 1612292SN/A#endif 1621060SN/A} 1631464SN/A 1642292SN/A#ifdef DEBUG 1652292SN/Atemplate <class Impl> 1662292SN/Avoid 1672292SN/ABaseDynInst<Impl>::dumpSNList() 1682292SN/A{ 1692292SN/A std::set<InstSeqNum>::iterator sn_it = cpu->snList.begin(); 1702292SN/A 1712292SN/A int count = 0; 1722292SN/A while (sn_it != cpu->snList.end()) { 1732292SN/A cprintf("%i: [sn:%lli] not destroyed\n", count, (*sn_it)); 1742292SN/A count++; 1752292SN/A sn_it++; 1762292SN/A } 1772292SN/A} 1782292SN/A#endif 1792292SN/A 1801061SN/Atemplate <class Impl> 1811060SN/Avoid 1821060SN/ABaseDynInst<Impl>::prefetch(Addr addr, unsigned flags) 1831060SN/A{ 1841060SN/A // This is the "functional" implementation of prefetch. Not much 1851060SN/A // happens here since prefetches don't affect the architectural 1861060SN/A // state. 1872669SN/A/* 1881060SN/A // Generate a MemReq so we can translate the effective address. 1892292SN/A MemReqPtr req = new MemReq(addr, thread->getXCProxy(), 1, flags); 1901060SN/A req->asid = asid; 1911060SN/A 1921060SN/A // Prefetches never cause faults. 1932090SN/A fault = NoFault; 1941060SN/A 1951060SN/A // note this is a local, not BaseDynInst::fault 1962292SN/A Fault trans_fault = cpu->translateDataReadReq(req); 1971060SN/A 1983172Sstever@eecs.umich.edu if (trans_fault == NoFault && !(req->isUncacheable())) { 1991060SN/A // It's a valid address to cacheable space. Record key MemReq 2001060SN/A // parameters so we can generate another one just like it for 2011060SN/A // the timing access without calling translate() again (which 2021060SN/A // might mess up the TLB). 2031060SN/A effAddr = req->vaddr; 2041060SN/A physEffAddr = req->paddr; 2051060SN/A memReqFlags = req->flags; 2061060SN/A } else { 2071060SN/A // Bogus address (invalid or uncacheable space). Mark it by 2081060SN/A // setting the eff_addr to InvalidAddr. 2091060SN/A effAddr = physEffAddr = MemReq::inval_addr; 2101060SN/A } 2111060SN/A 2121060SN/A if (traceData) { 2131060SN/A traceData->setAddr(addr); 2141060SN/A } 2152669SN/A*/ 2161060SN/A} 2171060SN/A 2181061SN/Atemplate <class Impl> 2191060SN/Avoid 2201060SN/ABaseDynInst<Impl>::writeHint(Addr addr, int size, unsigned flags) 2211060SN/A{ 2222702SN/A // Not currently supported. 2231060SN/A} 2241060SN/A 2251060SN/A/** 2261060SN/A * @todo Need to find a way to get the cache block size here. 2271060SN/A */ 2281061SN/Atemplate <class Impl> 2292132SN/AFault 2301060SN/ABaseDynInst<Impl>::copySrcTranslate(Addr src) 2311060SN/A{ 2322702SN/A // Not currently supported. 2332669SN/A return NoFault; 2341060SN/A} 2351060SN/A 2361060SN/A/** 2371060SN/A * @todo Need to find a way to get the cache block size here. 2381060SN/A */ 2391061SN/Atemplate <class Impl> 2402132SN/AFault 2411060SN/ABaseDynInst<Impl>::copy(Addr dest) 2421060SN/A{ 2432702SN/A // Not currently supported. 2442669SN/A return NoFault; 2451060SN/A} 2461060SN/A 2471061SN/Atemplate <class Impl> 2481060SN/Avoid 2491060SN/ABaseDynInst<Impl>::dump() 2501060SN/A{ 2511060SN/A cprintf("T%d : %#08d `", threadNumber, PC); 2522980Sgblack@eecs.umich.edu std::cout << staticInst->disassemble(PC); 2531060SN/A cprintf("'\n"); 2541060SN/A} 2551060SN/A 2561061SN/Atemplate <class Impl> 2571060SN/Avoid 2581060SN/ABaseDynInst<Impl>::dump(std::string &outstring) 2591060SN/A{ 2601060SN/A std::ostringstream s; 2611060SN/A s << "T" << threadNumber << " : 0x" << PC << " " 2621060SN/A << staticInst->disassemble(PC); 2631060SN/A 2641060SN/A outstring = s.str(); 2651060SN/A} 2661060SN/A 2671464SN/Atemplate <class Impl> 2682292SN/Avoid 2692292SN/ABaseDynInst<Impl>::markSrcRegReady() 2702292SN/A{ 2712292SN/A if (++readyRegs == numSrcRegs()) { 2724032Sktlim@umich.edu setCanIssue(); 2732292SN/A } 2742292SN/A} 2752292SN/A 2762292SN/Atemplate <class Impl> 2772292SN/Avoid 2782292SN/ABaseDynInst<Impl>::markSrcRegReady(RegIndex src_idx) 2792292SN/A{ 2802292SN/A _readySrcRegIdx[src_idx] = true; 2812292SN/A 2822731SN/A markSrcRegReady(); 2832292SN/A} 2842292SN/A 2852292SN/Atemplate <class Impl> 2861464SN/Abool 2871464SN/ABaseDynInst<Impl>::eaSrcsReady() 2881464SN/A{ 2891464SN/A // For now I am assuming that src registers 1..n-1 are the ones that the 2901464SN/A // EA calc depends on. (i.e. src reg 0 is the source of the data to be 2911464SN/A // stored) 2921464SN/A 2932292SN/A for (int i = 1; i < numSrcRegs(); ++i) { 2941464SN/A if (!_readySrcRegIdx[i]) 2951464SN/A return false; 2961464SN/A } 2971464SN/A 2981464SN/A return true; 2991464SN/A} 300