base_dyn_inst_impl.hh revision 3794
11060SN/A/* 22702SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31060SN/A * All rights reserved. 41060SN/A * 51060SN/A * Redistribution and use in source and binary forms, with or without 61060SN/A * modification, are permitted provided that the following conditions are 71060SN/A * met: redistributions of source code must retain the above copyright 81060SN/A * notice, this list of conditions and the following disclaimer; 91060SN/A * redistributions in binary form must reproduce the above copyright 101060SN/A * notice, this list of conditions and the following disclaimer in the 111060SN/A * documentation and/or other materials provided with the distribution; 121060SN/A * neither the name of the copyright holders nor the names of its 131060SN/A * contributors may be used to endorse or promote products derived from 141060SN/A * this software without specific prior written permission. 151060SN/A * 161060SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171060SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181060SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191060SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201060SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211060SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221060SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231060SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241060SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251060SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261060SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A * 282665SN/A * Authors: Kevin Lim 291060SN/A */ 301060SN/A 311060SN/A#include <iostream> 322292SN/A#include <set> 331060SN/A#include <string> 341060SN/A#include <sstream> 351060SN/A 361060SN/A#include "base/cprintf.hh" 371061SN/A#include "base/trace.hh" 381060SN/A 392980Sgblack@eecs.umich.edu#include "sim/faults.hh" 401060SN/A#include "cpu/exetrace.hh" 412669SN/A#include "mem/request.hh" 421060SN/A 431060SN/A#include "cpu/base_dyn_inst.hh" 441060SN/A 451060SN/A#define NOHASH 461060SN/A#ifndef NOHASH 471060SN/A 481060SN/A#include "base/hashmap.hh" 491060SN/A 501060SN/Aunsigned int MyHashFunc(const BaseDynInst *addr) 511060SN/A{ 522292SN/A unsigned a = (unsigned)addr; 532292SN/A unsigned hash = (((a >> 14) ^ ((a >> 2) & 0xffff))) & 0x7FFFFFFF; 541060SN/A 552292SN/A return hash; 561060SN/A} 571060SN/A 582292SN/Atypedef m5::hash_map<const BaseDynInst *, const BaseDynInst *, MyHashFunc> 592292SN/Amy_hash_t; 602292SN/A 611060SN/Amy_hash_t thishash; 621060SN/A#endif 631060SN/A 641061SN/Atemplate <class Impl> 652980Sgblack@eecs.umich.eduBaseDynInst<Impl>::BaseDynInst(TheISA::ExtMachInst machInst, Addr inst_PC, 663794Sgblack@eecs.umich.edu Addr pred_PC, Addr pred_NPC, 673794Sgblack@eecs.umich.edu InstSeqNum seq_num, ImplCPU *cpu) 682733SN/A : staticInst(machInst), traceData(NULL), cpu(cpu) 691060SN/A{ 701464SN/A seqNum = seq_num; 711061SN/A 721464SN/A PC = inst_PC; 732980Sgblack@eecs.umich.edu nextPC = PC + sizeof(TheISA::MachInst); 742980Sgblack@eecs.umich.edu nextNPC = nextPC + sizeof(TheISA::MachInst); 751464SN/A predPC = pred_PC; 763794Sgblack@eecs.umich.edu predNPC = pred_NPC; 773794Sgblack@eecs.umich.edu predTaken = false; 781464SN/A 791464SN/A initVars(); 801464SN/A} 811464SN/A 821464SN/Atemplate <class Impl> 832107SN/ABaseDynInst<Impl>::BaseDynInst(StaticInstPtr &_staticInst) 841464SN/A : staticInst(_staticInst), traceData(NULL) 851464SN/A{ 862292SN/A seqNum = 0; 871464SN/A initVars(); 881464SN/A} 891464SN/A 901464SN/Atemplate <class Impl> 911464SN/Avoid 921464SN/ABaseDynInst<Impl>::initVars() 931464SN/A{ 942292SN/A req = NULL; 952678SN/A memData = NULL; 962669SN/A effAddr = 0; 972669SN/A physEffAddr = 0; 981060SN/A 991060SN/A readyRegs = 0; 1001060SN/A 1012702SN/A instResult.integer = 0; 1023326Sktlim@umich.edu recordResult = true; 1032702SN/A 1042731SN/A status.reset(); 1052731SN/A 1061464SN/A eaCalcDone = false; 1072292SN/A memOpDone = false; 1082731SN/A 1092292SN/A lqIdx = -1; 1102292SN/A sqIdx = -1; 1112292SN/A 1121060SN/A // Eventually make this a parameter. 1131060SN/A threadNumber = 0; 1141464SN/A 1151060SN/A // Also make this a parameter, or perhaps get it from xc or cpu. 1161060SN/A asid = 0; 1171060SN/A 1182698SN/A // Initialize the fault to be NoFault. 1192292SN/A fault = NoFault; 1201060SN/A 1211060SN/A ++instcount; 1221060SN/A 1232292SN/A if (instcount > 1500) { 1242292SN/A cpu->dumpInsts(); 1252292SN/A#ifdef DEBUG 1262292SN/A dumpSNList(); 1272292SN/A#endif 1282292SN/A assert(instcount <= 1500); 1292292SN/A } 1302292SN/A 1312292SN/A DPRINTF(DynInst, "DynInst: [sn:%lli] Instruction created. Instcount=%i\n", 1322292SN/A seqNum, instcount); 1332292SN/A 1342292SN/A#ifdef DEBUG 1352292SN/A cpu->snList.insert(seqNum); 1362292SN/A#endif 1371060SN/A} 1381060SN/A 1391061SN/Atemplate <class Impl> 1401060SN/ABaseDynInst<Impl>::~BaseDynInst() 1411060SN/A{ 1422292SN/A if (req) { 1432678SN/A delete req; 1442678SN/A } 1452678SN/A 1462678SN/A if (memData) { 1472678SN/A delete [] memData; 1482292SN/A } 1492292SN/A 1502292SN/A if (traceData) { 1512292SN/A delete traceData; 1522292SN/A } 1532292SN/A 1542348SN/A fault = NoFault; 1552348SN/A 1561060SN/A --instcount; 1572292SN/A 1582292SN/A DPRINTF(DynInst, "DynInst: [sn:%lli] Instruction destroyed. Instcount=%i\n", 1592292SN/A seqNum, instcount); 1602292SN/A#ifdef DEBUG 1612292SN/A cpu->snList.erase(seqNum); 1622292SN/A#endif 1631060SN/A} 1641464SN/A 1652292SN/A#ifdef DEBUG 1662292SN/Atemplate <class Impl> 1672292SN/Avoid 1682292SN/ABaseDynInst<Impl>::dumpSNList() 1692292SN/A{ 1702292SN/A std::set<InstSeqNum>::iterator sn_it = cpu->snList.begin(); 1712292SN/A 1722292SN/A int count = 0; 1732292SN/A while (sn_it != cpu->snList.end()) { 1742292SN/A cprintf("%i: [sn:%lli] not destroyed\n", count, (*sn_it)); 1752292SN/A count++; 1762292SN/A sn_it++; 1772292SN/A } 1782292SN/A} 1792292SN/A#endif 1802292SN/A 1811061SN/Atemplate <class Impl> 1821060SN/Avoid 1831060SN/ABaseDynInst<Impl>::prefetch(Addr addr, unsigned flags) 1841060SN/A{ 1851060SN/A // This is the "functional" implementation of prefetch. Not much 1861060SN/A // happens here since prefetches don't affect the architectural 1871060SN/A // state. 1882669SN/A/* 1891060SN/A // Generate a MemReq so we can translate the effective address. 1902292SN/A MemReqPtr req = new MemReq(addr, thread->getXCProxy(), 1, flags); 1911060SN/A req->asid = asid; 1921060SN/A 1931060SN/A // Prefetches never cause faults. 1942090SN/A fault = NoFault; 1951060SN/A 1961060SN/A // note this is a local, not BaseDynInst::fault 1972292SN/A Fault trans_fault = cpu->translateDataReadReq(req); 1981060SN/A 1993172Sstever@eecs.umich.edu if (trans_fault == NoFault && !(req->isUncacheable())) { 2001060SN/A // It's a valid address to cacheable space. Record key MemReq 2011060SN/A // parameters so we can generate another one just like it for 2021060SN/A // the timing access without calling translate() again (which 2031060SN/A // might mess up the TLB). 2041060SN/A effAddr = req->vaddr; 2051060SN/A physEffAddr = req->paddr; 2061060SN/A memReqFlags = req->flags; 2071060SN/A } else { 2081060SN/A // Bogus address (invalid or uncacheable space). Mark it by 2091060SN/A // setting the eff_addr to InvalidAddr. 2101060SN/A effAddr = physEffAddr = MemReq::inval_addr; 2111060SN/A } 2121060SN/A 2131060SN/A if (traceData) { 2141060SN/A traceData->setAddr(addr); 2151060SN/A } 2162669SN/A*/ 2171060SN/A} 2181060SN/A 2191061SN/Atemplate <class Impl> 2201060SN/Avoid 2211060SN/ABaseDynInst<Impl>::writeHint(Addr addr, int size, unsigned flags) 2221060SN/A{ 2232702SN/A // Not currently supported. 2241060SN/A} 2251060SN/A 2261060SN/A/** 2271060SN/A * @todo Need to find a way to get the cache block size here. 2281060SN/A */ 2291061SN/Atemplate <class Impl> 2302132SN/AFault 2311060SN/ABaseDynInst<Impl>::copySrcTranslate(Addr src) 2321060SN/A{ 2332702SN/A // Not currently supported. 2342669SN/A return NoFault; 2351060SN/A} 2361060SN/A 2371060SN/A/** 2381060SN/A * @todo Need to find a way to get the cache block size here. 2391060SN/A */ 2401061SN/Atemplate <class Impl> 2412132SN/AFault 2421060SN/ABaseDynInst<Impl>::copy(Addr dest) 2431060SN/A{ 2442702SN/A // Not currently supported. 2452669SN/A return NoFault; 2461060SN/A} 2471060SN/A 2481061SN/Atemplate <class Impl> 2491060SN/Avoid 2501060SN/ABaseDynInst<Impl>::dump() 2511060SN/A{ 2521060SN/A cprintf("T%d : %#08d `", threadNumber, PC); 2532980Sgblack@eecs.umich.edu std::cout << staticInst->disassemble(PC); 2541060SN/A cprintf("'\n"); 2551060SN/A} 2561060SN/A 2571061SN/Atemplate <class Impl> 2581060SN/Avoid 2591060SN/ABaseDynInst<Impl>::dump(std::string &outstring) 2601060SN/A{ 2611060SN/A std::ostringstream s; 2621060SN/A s << "T" << threadNumber << " : 0x" << PC << " " 2631060SN/A << staticInst->disassemble(PC); 2641060SN/A 2651060SN/A outstring = s.str(); 2661060SN/A} 2671060SN/A 2681464SN/Atemplate <class Impl> 2692292SN/Avoid 2702292SN/ABaseDynInst<Impl>::markSrcRegReady() 2712292SN/A{ 2722292SN/A if (++readyRegs == numSrcRegs()) { 2732731SN/A status.set(CanIssue); 2742292SN/A } 2752292SN/A} 2762292SN/A 2772292SN/Atemplate <class Impl> 2782292SN/Avoid 2792292SN/ABaseDynInst<Impl>::markSrcRegReady(RegIndex src_idx) 2802292SN/A{ 2812292SN/A _readySrcRegIdx[src_idx] = true; 2822292SN/A 2832731SN/A markSrcRegReady(); 2842292SN/A} 2852292SN/A 2862292SN/Atemplate <class Impl> 2871464SN/Abool 2881464SN/ABaseDynInst<Impl>::eaSrcsReady() 2891464SN/A{ 2901464SN/A // For now I am assuming that src registers 1..n-1 are the ones that the 2911464SN/A // EA calc depends on. (i.e. src reg 0 is the source of the data to be 2921464SN/A // stored) 2931464SN/A 2942292SN/A for (int i = 1; i < numSrcRegs(); ++i) { 2951464SN/A if (!_readySrcRegIdx[i]) 2961464SN/A return false; 2971464SN/A } 2981464SN/A 2991464SN/A return true; 3001464SN/A} 301