base_dyn_inst_impl.hh revision 3172
11060SN/A/* 22702SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31060SN/A * All rights reserved. 41060SN/A * 51060SN/A * Redistribution and use in source and binary forms, with or without 61060SN/A * modification, are permitted provided that the following conditions are 71060SN/A * met: redistributions of source code must retain the above copyright 81060SN/A * notice, this list of conditions and the following disclaimer; 91060SN/A * redistributions in binary form must reproduce the above copyright 101060SN/A * notice, this list of conditions and the following disclaimer in the 111060SN/A * documentation and/or other materials provided with the distribution; 121060SN/A * neither the name of the copyright holders nor the names of its 131060SN/A * contributors may be used to endorse or promote products derived from 141060SN/A * this software without specific prior written permission. 151060SN/A * 161060SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171060SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181060SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191060SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201060SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211060SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221060SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231060SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241060SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251060SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261060SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A * 282665SN/A * Authors: Kevin Lim 291060SN/A */ 301060SN/A 311060SN/A#include <iostream> 322292SN/A#include <set> 331060SN/A#include <string> 341060SN/A#include <sstream> 351060SN/A 361060SN/A#include "base/cprintf.hh" 371061SN/A#include "base/trace.hh" 381060SN/A 392980Sgblack@eecs.umich.edu#include "sim/faults.hh" 401060SN/A#include "cpu/exetrace.hh" 412669SN/A#include "mem/request.hh" 421060SN/A 431060SN/A#include "cpu/base_dyn_inst.hh" 441060SN/A 451060SN/A#define NOHASH 461060SN/A#ifndef NOHASH 471060SN/A 481060SN/A#include "base/hashmap.hh" 491060SN/A 501060SN/Aunsigned int MyHashFunc(const BaseDynInst *addr) 511060SN/A{ 522292SN/A unsigned a = (unsigned)addr; 532292SN/A unsigned hash = (((a >> 14) ^ ((a >> 2) & 0xffff))) & 0x7FFFFFFF; 541060SN/A 552292SN/A return hash; 561060SN/A} 571060SN/A 582292SN/Atypedef m5::hash_map<const BaseDynInst *, const BaseDynInst *, MyHashFunc> 592292SN/Amy_hash_t; 602292SN/A 611060SN/Amy_hash_t thishash; 621060SN/A#endif 631060SN/A 641061SN/Atemplate <class Impl> 652980Sgblack@eecs.umich.eduBaseDynInst<Impl>::BaseDynInst(TheISA::ExtMachInst machInst, Addr inst_PC, 661060SN/A Addr pred_PC, InstSeqNum seq_num, 672733SN/A ImplCPU *cpu) 682733SN/A : staticInst(machInst), traceData(NULL), cpu(cpu) 691060SN/A{ 701464SN/A seqNum = seq_num; 711061SN/A 721464SN/A PC = inst_PC; 732980Sgblack@eecs.umich.edu nextPC = PC + sizeof(TheISA::MachInst); 742980Sgblack@eecs.umich.edu nextNPC = nextPC + sizeof(TheISA::MachInst); 751464SN/A predPC = pred_PC; 761464SN/A 771464SN/A initVars(); 781464SN/A} 791464SN/A 801464SN/Atemplate <class Impl> 812107SN/ABaseDynInst<Impl>::BaseDynInst(StaticInstPtr &_staticInst) 821464SN/A : staticInst(_staticInst), traceData(NULL) 831464SN/A{ 842292SN/A seqNum = 0; 851464SN/A initVars(); 861464SN/A} 871464SN/A 881464SN/Atemplate <class Impl> 891464SN/Avoid 901464SN/ABaseDynInst<Impl>::initVars() 911464SN/A{ 922292SN/A req = NULL; 932678SN/A memData = NULL; 942669SN/A effAddr = 0; 952669SN/A physEffAddr = 0; 961060SN/A 971060SN/A readyRegs = 0; 981060SN/A 992702SN/A instResult.integer = 0; 1002702SN/A 1012731SN/A status.reset(); 1022731SN/A 1031464SN/A eaCalcDone = false; 1042292SN/A memOpDone = false; 1052731SN/A 1062292SN/A lqIdx = -1; 1072292SN/A sqIdx = -1; 1082292SN/A 1091060SN/A // Eventually make this a parameter. 1101060SN/A threadNumber = 0; 1111464SN/A 1121060SN/A // Also make this a parameter, or perhaps get it from xc or cpu. 1131060SN/A asid = 0; 1141060SN/A 1152698SN/A // Initialize the fault to be NoFault. 1162292SN/A fault = NoFault; 1171060SN/A 1181060SN/A ++instcount; 1191060SN/A 1202292SN/A if (instcount > 1500) { 1212292SN/A cpu->dumpInsts(); 1222292SN/A#ifdef DEBUG 1232292SN/A dumpSNList(); 1242292SN/A#endif 1252292SN/A assert(instcount <= 1500); 1262292SN/A } 1272292SN/A 1282292SN/A DPRINTF(DynInst, "DynInst: [sn:%lli] Instruction created. Instcount=%i\n", 1292292SN/A seqNum, instcount); 1302292SN/A 1312292SN/A#ifdef DEBUG 1322292SN/A cpu->snList.insert(seqNum); 1332292SN/A#endif 1341060SN/A} 1351060SN/A 1361061SN/Atemplate <class Impl> 1371060SN/ABaseDynInst<Impl>::~BaseDynInst() 1381060SN/A{ 1392292SN/A if (req) { 1402678SN/A delete req; 1412678SN/A } 1422678SN/A 1432678SN/A if (memData) { 1442678SN/A delete [] memData; 1452292SN/A } 1462292SN/A 1472292SN/A if (traceData) { 1482292SN/A delete traceData; 1492292SN/A } 1502292SN/A 1512348SN/A fault = NoFault; 1522348SN/A 1531060SN/A --instcount; 1542292SN/A 1552292SN/A DPRINTF(DynInst, "DynInst: [sn:%lli] Instruction destroyed. Instcount=%i\n", 1562292SN/A seqNum, instcount); 1572292SN/A#ifdef DEBUG 1582292SN/A cpu->snList.erase(seqNum); 1592292SN/A#endif 1601060SN/A} 1611464SN/A 1622292SN/A#ifdef DEBUG 1632292SN/Atemplate <class Impl> 1642292SN/Avoid 1652292SN/ABaseDynInst<Impl>::dumpSNList() 1662292SN/A{ 1672292SN/A std::set<InstSeqNum>::iterator sn_it = cpu->snList.begin(); 1682292SN/A 1692292SN/A int count = 0; 1702292SN/A while (sn_it != cpu->snList.end()) { 1712292SN/A cprintf("%i: [sn:%lli] not destroyed\n", count, (*sn_it)); 1722292SN/A count++; 1732292SN/A sn_it++; 1742292SN/A } 1752292SN/A} 1762292SN/A#endif 1772292SN/A 1781061SN/Atemplate <class Impl> 1791060SN/Avoid 1801060SN/ABaseDynInst<Impl>::prefetch(Addr addr, unsigned flags) 1811060SN/A{ 1821060SN/A // This is the "functional" implementation of prefetch. Not much 1831060SN/A // happens here since prefetches don't affect the architectural 1841060SN/A // state. 1852669SN/A/* 1861060SN/A // Generate a MemReq so we can translate the effective address. 1872292SN/A MemReqPtr req = new MemReq(addr, thread->getXCProxy(), 1, flags); 1881060SN/A req->asid = asid; 1891060SN/A 1901060SN/A // Prefetches never cause faults. 1912090SN/A fault = NoFault; 1921060SN/A 1931060SN/A // note this is a local, not BaseDynInst::fault 1942292SN/A Fault trans_fault = cpu->translateDataReadReq(req); 1951060SN/A 1963172Sstever@eecs.umich.edu if (trans_fault == NoFault && !(req->isUncacheable())) { 1971060SN/A // It's a valid address to cacheable space. Record key MemReq 1981060SN/A // parameters so we can generate another one just like it for 1991060SN/A // the timing access without calling translate() again (which 2001060SN/A // might mess up the TLB). 2011060SN/A effAddr = req->vaddr; 2021060SN/A physEffAddr = req->paddr; 2031060SN/A memReqFlags = req->flags; 2041060SN/A } else { 2051060SN/A // Bogus address (invalid or uncacheable space). Mark it by 2061060SN/A // setting the eff_addr to InvalidAddr. 2071060SN/A effAddr = physEffAddr = MemReq::inval_addr; 2081060SN/A } 2091060SN/A 2101060SN/A if (traceData) { 2111060SN/A traceData->setAddr(addr); 2121060SN/A } 2132669SN/A*/ 2141060SN/A} 2151060SN/A 2161061SN/Atemplate <class Impl> 2171060SN/Avoid 2181060SN/ABaseDynInst<Impl>::writeHint(Addr addr, int size, unsigned flags) 2191060SN/A{ 2202702SN/A // Not currently supported. 2211060SN/A} 2221060SN/A 2231060SN/A/** 2241060SN/A * @todo Need to find a way to get the cache block size here. 2251060SN/A */ 2261061SN/Atemplate <class Impl> 2272132SN/AFault 2281060SN/ABaseDynInst<Impl>::copySrcTranslate(Addr src) 2291060SN/A{ 2302702SN/A // Not currently supported. 2312669SN/A return NoFault; 2321060SN/A} 2331060SN/A 2341060SN/A/** 2351060SN/A * @todo Need to find a way to get the cache block size here. 2361060SN/A */ 2371061SN/Atemplate <class Impl> 2382132SN/AFault 2391060SN/ABaseDynInst<Impl>::copy(Addr dest) 2401060SN/A{ 2412702SN/A // Not currently supported. 2422669SN/A return NoFault; 2431060SN/A} 2441060SN/A 2451061SN/Atemplate <class Impl> 2461060SN/Avoid 2471060SN/ABaseDynInst<Impl>::dump() 2481060SN/A{ 2491060SN/A cprintf("T%d : %#08d `", threadNumber, PC); 2502980Sgblack@eecs.umich.edu std::cout << staticInst->disassemble(PC); 2511060SN/A cprintf("'\n"); 2521060SN/A} 2531060SN/A 2541061SN/Atemplate <class Impl> 2551060SN/Avoid 2561060SN/ABaseDynInst<Impl>::dump(std::string &outstring) 2571060SN/A{ 2581060SN/A std::ostringstream s; 2591060SN/A s << "T" << threadNumber << " : 0x" << PC << " " 2601060SN/A << staticInst->disassemble(PC); 2611060SN/A 2621060SN/A outstring = s.str(); 2631060SN/A} 2641060SN/A 2651464SN/Atemplate <class Impl> 2662292SN/Avoid 2672292SN/ABaseDynInst<Impl>::markSrcRegReady() 2682292SN/A{ 2692292SN/A if (++readyRegs == numSrcRegs()) { 2702731SN/A status.set(CanIssue); 2712292SN/A } 2722292SN/A} 2732292SN/A 2742292SN/Atemplate <class Impl> 2752292SN/Avoid 2762292SN/ABaseDynInst<Impl>::markSrcRegReady(RegIndex src_idx) 2772292SN/A{ 2782292SN/A _readySrcRegIdx[src_idx] = true; 2792292SN/A 2802731SN/A markSrcRegReady(); 2812292SN/A} 2822292SN/A 2832292SN/Atemplate <class Impl> 2841464SN/Abool 2851464SN/ABaseDynInst<Impl>::eaSrcsReady() 2861464SN/A{ 2871464SN/A // For now I am assuming that src registers 1..n-1 are the ones that the 2881464SN/A // EA calc depends on. (i.e. src reg 0 is the source of the data to be 2891464SN/A // stored) 2901464SN/A 2912292SN/A for (int i = 1; i < numSrcRegs(); ++i) { 2921464SN/A if (!_readySrcRegIdx[i]) 2931464SN/A return false; 2941464SN/A } 2951464SN/A 2961464SN/A return true; 2971464SN/A} 298