base_dyn_inst_impl.hh revision 13453
11060SN/A/* 27944SGiacomo.Gabrielli@arm.com * Copyright (c) 2011 ARM Limited 37944SGiacomo.Gabrielli@arm.com * All rights reserved. 47944SGiacomo.Gabrielli@arm.com * 57944SGiacomo.Gabrielli@arm.com * The license below extends only to copyright in the software and shall 67944SGiacomo.Gabrielli@arm.com * not be construed as granting a license to any other intellectual 77944SGiacomo.Gabrielli@arm.com * property including but not limited to intellectual property relating 87944SGiacomo.Gabrielli@arm.com * to a hardware implementation of the functionality of the software 97944SGiacomo.Gabrielli@arm.com * licensed hereunder. You may use the software subject to the license 107944SGiacomo.Gabrielli@arm.com * terms below provided that you ensure that this notice is replicated 117944SGiacomo.Gabrielli@arm.com * unmodified and in its entirety in all distributions of the software, 127944SGiacomo.Gabrielli@arm.com * modified or unmodified, in source code or in binary form. 137944SGiacomo.Gabrielli@arm.com * 142702SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 151060SN/A * All rights reserved. 161060SN/A * 171060SN/A * Redistribution and use in source and binary forms, with or without 181060SN/A * modification, are permitted provided that the following conditions are 191060SN/A * met: redistributions of source code must retain the above copyright 201060SN/A * notice, this list of conditions and the following disclaimer; 211060SN/A * redistributions in binary form must reproduce the above copyright 221060SN/A * notice, this list of conditions and the following disclaimer in the 231060SN/A * documentation and/or other materials provided with the distribution; 241060SN/A * neither the name of the copyright holders nor the names of its 251060SN/A * contributors may be used to endorse or promote products derived from 261060SN/A * this software without specific prior written permission. 271060SN/A * 281060SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 291060SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 301060SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 311060SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 321060SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 331060SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 341060SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 351060SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 361060SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 371060SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 381060SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665SN/A * 402665SN/A * Authors: Kevin Lim 411060SN/A */ 421060SN/A 439944Smatt.horsnell@ARM.com#ifndef __CPU_BASE_DYN_INST_IMPL_HH__ 449944Smatt.horsnell@ARM.com#define __CPU_BASE_DYN_INST_IMPL_HH__ 459944Smatt.horsnell@ARM.com 461060SN/A#include <iostream> 472292SN/A#include <set> 488229Snate@binkert.org#include <sstream> 491060SN/A#include <string> 501060SN/A 511060SN/A#include "base/cprintf.hh" 521061SN/A#include "base/trace.hh" 536658Snate@binkert.org#include "config/the_isa.hh" 546658Snate@binkert.org#include "cpu/base_dyn_inst.hh" 551060SN/A#include "cpu/exetrace.hh" 568232Snate@binkert.org#include "debug/DynInst.hh" 578232Snate@binkert.org#include "debug/IQ.hh" 582669SN/A#include "mem/request.hh" 596658Snate@binkert.org#include "sim/faults.hh" 601060SN/A 611061SN/Atemplate <class Impl> 6210417Sandreas.hansson@arm.comBaseDynInst<Impl>::BaseDynInst(const StaticInstPtr &_staticInst, 6310417Sandreas.hansson@arm.com const StaticInstPtr &_macroop, 647720Sgblack@eecs.umich.edu TheISA::PCState _pc, TheISA::PCState _predPC, 653794Sgblack@eecs.umich.edu InstSeqNum seq_num, ImplCPU *cpu) 6613453Srekai.gonzalezalberquilla@arm.com : staticInst(_staticInst), cpu(cpu), 6713453Srekai.gonzalezalberquilla@arm.com thread(nullptr), 6813453Srekai.gonzalezalberquilla@arm.com traceData(nullptr), 6913453Srekai.gonzalezalberquilla@arm.com macroop(_macroop), 7013453Srekai.gonzalezalberquilla@arm.com memData(nullptr), 7113453Srekai.gonzalezalberquilla@arm.com savedReq(nullptr), 7213453Srekai.gonzalezalberquilla@arm.com savedSreqLow(nullptr), 7313453Srekai.gonzalezalberquilla@arm.com savedSreqHigh(nullptr), 7413453Srekai.gonzalezalberquilla@arm.com reqToVerify(nullptr) 751060SN/A{ 761464SN/A seqNum = seq_num; 771061SN/A 787720Sgblack@eecs.umich.edu pc = _pc; 797720Sgblack@eecs.umich.edu predPC = _predPC; 804636Sgblack@eecs.umich.edu 814636Sgblack@eecs.umich.edu initVars(); 824636Sgblack@eecs.umich.edu} 834636Sgblack@eecs.umich.edu 844636Sgblack@eecs.umich.edutemplate <class Impl> 8510417Sandreas.hansson@arm.comBaseDynInst<Impl>::BaseDynInst(const StaticInstPtr &_staticInst, 8610417Sandreas.hansson@arm.com const StaticInstPtr &_macroop) 879046SAli.Saidi@ARM.com : staticInst(_staticInst), traceData(NULL), macroop(_macroop) 881464SN/A{ 892292SN/A seqNum = 0; 901464SN/A initVars(); 911464SN/A} 921464SN/A 931464SN/Atemplate <class Impl> 941464SN/Avoid 951464SN/ABaseDynInst<Impl>::initVars() 961464SN/A{ 972678SN/A memData = NULL; 982669SN/A effAddr = 0; 9911097Songal@cs.wisc.edu physEffAddrLow = 0; 10011097Songal@cs.wisc.edu physEffAddrHigh = 0; 1011060SN/A readyRegs = 0; 10210031SAli.Saidi@ARM.com memReqFlags = 0; 1031060SN/A 1042731SN/A status.reset(); 1052731SN/A 1069046SAli.Saidi@ARM.com instFlags.reset(); 1079046SAli.Saidi@ARM.com instFlags[RecordResult] = true; 1089046SAli.Saidi@ARM.com instFlags[Predicate] = true; 1092731SN/A 1102292SN/A lqIdx = -1; 1112292SN/A sqIdx = -1; 1122292SN/A 1131060SN/A // Eventually make this a parameter. 1141060SN/A threadNumber = 0; 1151464SN/A 1161060SN/A // Also make this a parameter, or perhaps get it from xc or cpu. 1171060SN/A asid = 0; 1181060SN/A 1192698SN/A // Initialize the fault to be NoFault. 1202292SN/A fault = NoFault; 1211060SN/A 1225737Scws3k@cs.virginia.edu#ifndef NDEBUG 1235737Scws3k@cs.virginia.edu ++cpu->instcount; 1241060SN/A 1255737Scws3k@cs.virginia.edu if (cpu->instcount > 1500) { 1265375Svilas.sridharan@gmail.com#ifdef DEBUG 1272292SN/A cpu->dumpInsts(); 1282292SN/A dumpSNList(); 1292292SN/A#endif 1305737Scws3k@cs.virginia.edu assert(cpu->instcount <= 1500); 1312292SN/A } 1322292SN/A 1335737Scws3k@cs.virginia.edu DPRINTF(DynInst, 1345737Scws3k@cs.virginia.edu "DynInst: [sn:%lli] Instruction created. Instcount for %s = %i\n", 1355737Scws3k@cs.virginia.edu seqNum, cpu->name(), cpu->instcount); 1365737Scws3k@cs.virginia.edu#endif 1372292SN/A 1382292SN/A#ifdef DEBUG 1392292SN/A cpu->snList.insert(seqNum); 1402292SN/A#endif 1418733Sgeoffrey.blake@arm.com 1421060SN/A} 1431060SN/A 1441061SN/Atemplate <class Impl> 1451060SN/ABaseDynInst<Impl>::~BaseDynInst() 1461060SN/A{ 1472678SN/A if (memData) { 1482678SN/A delete [] memData; 1492292SN/A } 1502292SN/A 1512292SN/A if (traceData) { 1522292SN/A delete traceData; 1532292SN/A } 1542292SN/A 1552348SN/A fault = NoFault; 1562348SN/A 1575737Scws3k@cs.virginia.edu#ifndef NDEBUG 1585737Scws3k@cs.virginia.edu --cpu->instcount; 1592292SN/A 1605737Scws3k@cs.virginia.edu DPRINTF(DynInst, 1615737Scws3k@cs.virginia.edu "DynInst: [sn:%lli] Instruction destroyed. Instcount for %s = %i\n", 1625737Scws3k@cs.virginia.edu seqNum, cpu->name(), cpu->instcount); 1635737Scws3k@cs.virginia.edu#endif 1642292SN/A#ifdef DEBUG 1652292SN/A cpu->snList.erase(seqNum); 1662292SN/A#endif 1678733Sgeoffrey.blake@arm.com 1681060SN/A} 1691464SN/A 1702292SN/A#ifdef DEBUG 1712292SN/Atemplate <class Impl> 1722292SN/Avoid 1732292SN/ABaseDynInst<Impl>::dumpSNList() 1742292SN/A{ 1752292SN/A std::set<InstSeqNum>::iterator sn_it = cpu->snList.begin(); 1762292SN/A 1772292SN/A int count = 0; 1782292SN/A while (sn_it != cpu->snList.end()) { 1792292SN/A cprintf("%i: [sn:%lli] not destroyed\n", count, (*sn_it)); 1802292SN/A count++; 1812292SN/A sn_it++; 1822292SN/A } 1832292SN/A} 1842292SN/A#endif 1852292SN/A 1861061SN/Atemplate <class Impl> 1871060SN/Avoid 1881060SN/ABaseDynInst<Impl>::dump() 1891060SN/A{ 1907720Sgblack@eecs.umich.edu cprintf("T%d : %#08d `", threadNumber, pc.instAddr()); 1917720Sgblack@eecs.umich.edu std::cout << staticInst->disassemble(pc.instAddr()); 1921060SN/A cprintf("'\n"); 1931060SN/A} 1941060SN/A 1951061SN/Atemplate <class Impl> 1961060SN/Avoid 1971060SN/ABaseDynInst<Impl>::dump(std::string &outstring) 1981060SN/A{ 1991060SN/A std::ostringstream s; 2007720Sgblack@eecs.umich.edu s << "T" << threadNumber << " : 0x" << pc.instAddr() << " " 2017720Sgblack@eecs.umich.edu << staticInst->disassemble(pc.instAddr()); 2021060SN/A 2031060SN/A outstring = s.str(); 2041060SN/A} 2051060SN/A 2061464SN/Atemplate <class Impl> 2072292SN/Avoid 2082292SN/ABaseDynInst<Impl>::markSrcRegReady() 2092292SN/A{ 2107599Sminkyu.jeong@arm.com DPRINTF(IQ, "[sn:%lli] has %d ready out of %d sources. RTI %d)\n", 2117599Sminkyu.jeong@arm.com seqNum, readyRegs+1, numSrcRegs(), readyToIssue()); 2122292SN/A if (++readyRegs == numSrcRegs()) { 2134032Sktlim@umich.edu setCanIssue(); 2142292SN/A } 2152292SN/A} 2162292SN/A 2172292SN/Atemplate <class Impl> 2182292SN/Avoid 2192292SN/ABaseDynInst<Impl>::markSrcRegReady(RegIndex src_idx) 2202292SN/A{ 2212292SN/A _readySrcRegIdx[src_idx] = true; 2222292SN/A 2232731SN/A markSrcRegReady(); 2242292SN/A} 2252292SN/A 2262292SN/Atemplate <class Impl> 2271464SN/Abool 22813429Srekai.gonzalezalberquilla@arm.comBaseDynInst<Impl>::eaSrcsReady() const 2291464SN/A{ 2301464SN/A // For now I am assuming that src registers 1..n-1 are the ones that the 2311464SN/A // EA calc depends on. (i.e. src reg 0 is the source of the data to be 2321464SN/A // stored) 2331464SN/A 2342292SN/A for (int i = 1; i < numSrcRegs(); ++i) { 2351464SN/A if (!_readySrcRegIdx[i]) 2361464SN/A return false; 2371464SN/A } 2381464SN/A 2391464SN/A return true; 2401464SN/A} 2419944Smatt.horsnell@ARM.com 2429944Smatt.horsnell@ARM.com#endif//__CPU_BASE_DYN_INST_IMPL_HH__ 243