base_dyn_inst.hh revision 7678
11060SN/A/* 22702Sktlim@umich.edu * Copyright (c) 2004-2006 The Regents of The University of Michigan 36973Stjones1@inf.ed.ac.uk * Copyright (c) 2009 The University of Edinburgh 41060SN/A * All rights reserved. 51060SN/A * 61060SN/A * Redistribution and use in source and binary forms, with or without 71060SN/A * modification, are permitted provided that the following conditions are 81060SN/A * met: redistributions of source code must retain the above copyright 91060SN/A * notice, this list of conditions and the following disclaimer; 101060SN/A * redistributions in binary form must reproduce the above copyright 111060SN/A * notice, this list of conditions and the following disclaimer in the 121060SN/A * documentation and/or other materials provided with the distribution; 131060SN/A * neither the name of the copyright holders nor the names of its 141060SN/A * contributors may be used to endorse or promote products derived from 151060SN/A * this software without specific prior written permission. 161060SN/A * 171060SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 181060SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 191060SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 201060SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 211060SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 221060SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 231060SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 241060SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 251060SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 261060SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 271060SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282665Ssaidi@eecs.umich.edu * 292665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 306973Stjones1@inf.ed.ac.uk * Timothy M. Jones 311060SN/A */ 321060SN/A 331464SN/A#ifndef __CPU_BASE_DYN_INST_HH__ 341464SN/A#define __CPU_BASE_DYN_INST_HH__ 351060SN/A 362731Sktlim@umich.edu#include <bitset> 372292SN/A#include <list> 381464SN/A#include <string> 391060SN/A 402669Sktlim@umich.edu#include "arch/faults.hh" 411060SN/A#include "base/fast_alloc.hh" 421060SN/A#include "base/trace.hh" 431858SN/A#include "config/full_system.hh" 446658Snate@binkert.org#include "config/the_isa.hh" 453770Sgblack@eecs.umich.edu#include "cpu/o3/comm.hh" 461464SN/A#include "cpu/exetrace.hh" 471464SN/A#include "cpu/inst_seq.hh" 482669Sktlim@umich.edu#include "cpu/op_class.hh" 491060SN/A#include "cpu/static_inst.hh" 506973Stjones1@inf.ed.ac.uk#include "cpu/translation.hh" 512669Sktlim@umich.edu#include "mem/packet.hh" 527678Sgblack@eecs.umich.edu#include "sim/byteswap.hh" 532292SN/A#include "sim/system.hh" 546023Snate@binkert.org#include "sim/tlb.hh" 551060SN/A 561060SN/A/** 571060SN/A * @file 581060SN/A * Defines a dynamic instruction context. 591060SN/A */ 601060SN/A 611061SN/A// Forward declaration. 621061SN/Aclass StaticInstPtr; 631060SN/A 641060SN/Atemplate <class Impl> 651061SN/Aclass BaseDynInst : public FastAlloc, public RefCounted 661060SN/A{ 671060SN/A public: 681060SN/A // Typedef for the CPU. 692733Sktlim@umich.edu typedef typename Impl::CPUType ImplCPU; 702733Sktlim@umich.edu typedef typename ImplCPU::ImplState ImplState; 711060SN/A 722292SN/A // Logical register index type. 732107SN/A typedef TheISA::RegIndex RegIndex; 742690Sktlim@umich.edu // Integer register type. 752107SN/A typedef TheISA::IntReg IntReg; 762690Sktlim@umich.edu // Floating point register type. 772690Sktlim@umich.edu typedef TheISA::FloatReg FloatReg; 781060SN/A 792292SN/A // The DynInstPtr type. 802292SN/A typedef typename Impl::DynInstPtr DynInstPtr; 812292SN/A 822292SN/A // The list of instructions iterator type. 832292SN/A typedef typename std::list<DynInstPtr>::iterator ListIt; 842292SN/A 851060SN/A enum { 865543Ssaidi@eecs.umich.edu MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs 875543Ssaidi@eecs.umich.edu MaxInstDestRegs = TheISA::MaxInstDestRegs, /// Max dest regs 881060SN/A }; 891060SN/A 902292SN/A /** The StaticInst used by this BaseDynInst. */ 912107SN/A StaticInstPtr staticInst; 921060SN/A 931060SN/A //////////////////////////////////////////// 941060SN/A // 951060SN/A // INSTRUCTION EXECUTION 961060SN/A // 971060SN/A //////////////////////////////////////////// 982292SN/A /** InstRecord that tracks this instructions. */ 991060SN/A Trace::InstRecord *traceData; 1001060SN/A 1015358Sgblack@eecs.umich.edu void demapPage(Addr vaddr, uint64_t asn) 1025358Sgblack@eecs.umich.edu { 1035358Sgblack@eecs.umich.edu cpu->demapPage(vaddr, asn); 1045358Sgblack@eecs.umich.edu } 1055358Sgblack@eecs.umich.edu void demapInstPage(Addr vaddr, uint64_t asn) 1065358Sgblack@eecs.umich.edu { 1075358Sgblack@eecs.umich.edu cpu->demapPage(vaddr, asn); 1085358Sgblack@eecs.umich.edu } 1095358Sgblack@eecs.umich.edu void demapDataPage(Addr vaddr, uint64_t asn) 1105358Sgblack@eecs.umich.edu { 1115358Sgblack@eecs.umich.edu cpu->demapPage(vaddr, asn); 1125358Sgblack@eecs.umich.edu } 1135358Sgblack@eecs.umich.edu 1142292SN/A /** 1152292SN/A * Does a read to a given address. 1162292SN/A * @param addr The address to read. 1172292SN/A * @param data The read's data is written into this parameter. 1182292SN/A * @param flags The request's flags. 1192292SN/A * @return Returns any fault due to the read. 1202292SN/A */ 1211060SN/A template <class T> 1222132SN/A Fault read(Addr addr, T &data, unsigned flags); 1231060SN/A 1247520Sgblack@eecs.umich.edu Fault readBytes(Addr addr, uint8_t *data, unsigned size, unsigned flags); 1257520Sgblack@eecs.umich.edu 1262292SN/A /** 1272292SN/A * Does a write to a given address. 1282292SN/A * @param data The data to be written. 1292292SN/A * @param addr The address to write to. 1302292SN/A * @param flags The request's flags. 1312292SN/A * @param res The result of the write (for load locked/store conditionals). 1322292SN/A * @return Returns any fault due to the write. 1332292SN/A */ 1341060SN/A template <class T> 1356973Stjones1@inf.ed.ac.uk Fault write(T data, Addr addr, unsigned flags, uint64_t *res); 1366973Stjones1@inf.ed.ac.uk 1377520Sgblack@eecs.umich.edu Fault writeBytes(uint8_t *data, unsigned size, 1387520Sgblack@eecs.umich.edu Addr addr, unsigned flags, uint64_t *res); 1397520Sgblack@eecs.umich.edu 1406974Stjones1@inf.ed.ac.uk /** Splits a request in two if it crosses a dcache block. */ 1416974Stjones1@inf.ed.ac.uk void splitRequest(RequestPtr req, RequestPtr &sreqLow, 1426974Stjones1@inf.ed.ac.uk RequestPtr &sreqHigh); 1436974Stjones1@inf.ed.ac.uk 1446973Stjones1@inf.ed.ac.uk /** Initiate a DTB address translation. */ 1456974Stjones1@inf.ed.ac.uk void initiateTranslation(RequestPtr req, RequestPtr sreqLow, 1466974Stjones1@inf.ed.ac.uk RequestPtr sreqHigh, uint64_t *res, 1476973Stjones1@inf.ed.ac.uk BaseTLB::Mode mode); 1486973Stjones1@inf.ed.ac.uk 1496973Stjones1@inf.ed.ac.uk /** Finish a DTB address translation. */ 1506973Stjones1@inf.ed.ac.uk void finishTranslation(WholeTranslationState *state); 1511060SN/A 1521060SN/A void prefetch(Addr addr, unsigned flags); 1531060SN/A void writeHint(Addr addr, int size, unsigned flags); 1542132SN/A Fault copySrcTranslate(Addr src); 1552132SN/A Fault copy(Addr dest); 1561060SN/A 1571684SN/A /** @todo: Consider making this private. */ 1581060SN/A public: 1591060SN/A /** The sequence number of the instruction. */ 1601060SN/A InstSeqNum seqNum; 1611060SN/A 1622731Sktlim@umich.edu enum Status { 1632731Sktlim@umich.edu IqEntry, /// Instruction is in the IQ 1642731Sktlim@umich.edu RobEntry, /// Instruction is in the ROB 1652731Sktlim@umich.edu LsqEntry, /// Instruction is in the LSQ 1662731Sktlim@umich.edu Completed, /// Instruction has completed 1672731Sktlim@umich.edu ResultReady, /// Instruction has its result 1682731Sktlim@umich.edu CanIssue, /// Instruction can issue and execute 1692731Sktlim@umich.edu Issued, /// Instruction has issued 1702731Sktlim@umich.edu Executed, /// Instruction has executed 1712731Sktlim@umich.edu CanCommit, /// Instruction can commit 1722731Sktlim@umich.edu AtCommit, /// Instruction has reached commit 1732731Sktlim@umich.edu Committed, /// Instruction has committed 1742731Sktlim@umich.edu Squashed, /// Instruction is squashed 1752731Sktlim@umich.edu SquashedInIQ, /// Instruction is squashed in the IQ 1762731Sktlim@umich.edu SquashedInLSQ, /// Instruction is squashed in the LSQ 1772731Sktlim@umich.edu SquashedInROB, /// Instruction is squashed in the ROB 1782731Sktlim@umich.edu RecoverInst, /// Is a recover instruction 1792731Sktlim@umich.edu BlockingInst, /// Is a blocking instruction 1802731Sktlim@umich.edu ThreadsyncWait, /// Is a thread synchronization instruction 1812731Sktlim@umich.edu SerializeBefore, /// Needs to serialize on 1822731Sktlim@umich.edu /// instructions ahead of it 1832731Sktlim@umich.edu SerializeAfter, /// Needs to serialize instructions behind it 1842731Sktlim@umich.edu SerializeHandled, /// Serialization has been handled 1852731Sktlim@umich.edu NumStatus 1862731Sktlim@umich.edu }; 1872292SN/A 1882731Sktlim@umich.edu /** The status of this BaseDynInst. Several bits can be set. */ 1892731Sktlim@umich.edu std::bitset<NumStatus> status; 1901060SN/A 1911060SN/A /** The thread this instruction is from. */ 1926221Snate@binkert.org ThreadID threadNumber; 1931060SN/A 1941060SN/A /** data address space ID, for loads & stores. */ 1951060SN/A short asid; 1961060SN/A 1972292SN/A /** How many source registers are ready. */ 1982292SN/A unsigned readyRegs; 1992292SN/A 2002733Sktlim@umich.edu /** Pointer to the Impl's CPU object. */ 2012733Sktlim@umich.edu ImplCPU *cpu; 2021060SN/A 2032680Sktlim@umich.edu /** Pointer to the thread state. */ 2042292SN/A ImplState *thread; 2051060SN/A 2061060SN/A /** The kind of fault this instruction has generated. */ 2072132SN/A Fault fault; 2081060SN/A 2092702Sktlim@umich.edu /** Pointer to the data for the memory access. */ 2102669Sktlim@umich.edu uint8_t *memData; 2112292SN/A 2121060SN/A /** The effective virtual address (lds & stores only). */ 2131060SN/A Addr effAddr; 2141060SN/A 2154032Sktlim@umich.edu /** Is the effective virtual address valid. */ 2164032Sktlim@umich.edu bool effAddrValid; 2174032Sktlim@umich.edu 2181060SN/A /** The effective physical address. */ 2191060SN/A Addr physEffAddr; 2201060SN/A 2211060SN/A /** Effective virtual address for a copy source. */ 2221060SN/A Addr copySrcEffAddr; 2231060SN/A 2241060SN/A /** Effective physical address for a copy source. */ 2251060SN/A Addr copySrcPhysEffAddr; 2261060SN/A 2271060SN/A /** The memory request flags (from translation). */ 2281060SN/A unsigned memReqFlags; 2291060SN/A 2301464SN/A union Result { 2311464SN/A uint64_t integer; 2322356SN/A// float fp; 2331464SN/A double dbl; 2341464SN/A }; 2351060SN/A 2361464SN/A /** The result of the instruction; assumes for now that there's only one 2371464SN/A * destination register. 2381464SN/A */ 2391464SN/A Result instResult; 2401060SN/A 2413326Sktlim@umich.edu /** Records changes to result? */ 2423326Sktlim@umich.edu bool recordResult; 2433326Sktlim@umich.edu 2441060SN/A /** PC of this instruction. */ 2451060SN/A Addr PC; 2461060SN/A 2474636Sgblack@eecs.umich.edu /** Micro PC of this instruction. */ 2484636Sgblack@eecs.umich.edu Addr microPC; 2494636Sgblack@eecs.umich.edu 2507597Sminkyu.jeong@arm.com /** Did this instruction execute, or is it predicated false */ 2517597Sminkyu.jeong@arm.com bool predicate; 2527597Sminkyu.jeong@arm.com 2533965Sgblack@eecs.umich.edu protected: 2541060SN/A /** Next non-speculative PC. It is not filled in at fetch, but rather 2551060SN/A * once the target of the branch is truly known (either decode or 2561060SN/A * execute). 2571060SN/A */ 2581060SN/A Addr nextPC; 2591060SN/A 2602935Sksewell@umich.edu /** Next non-speculative NPC. Target PC for Mips or Sparc. */ 2612935Sksewell@umich.edu Addr nextNPC; 2622935Sksewell@umich.edu 2634636Sgblack@eecs.umich.edu /** Next non-speculative micro PC. */ 2644636Sgblack@eecs.umich.edu Addr nextMicroPC; 2654636Sgblack@eecs.umich.edu 2661060SN/A /** Predicted next PC. */ 2671060SN/A Addr predPC; 2681060SN/A 2693794Sgblack@eecs.umich.edu /** Predicted next NPC. */ 2703794Sgblack@eecs.umich.edu Addr predNPC; 2713794Sgblack@eecs.umich.edu 2724636Sgblack@eecs.umich.edu /** Predicted next microPC */ 2734636Sgblack@eecs.umich.edu Addr predMicroPC; 2744636Sgblack@eecs.umich.edu 2753794Sgblack@eecs.umich.edu /** If this is a branch that was predicted taken */ 2763794Sgblack@eecs.umich.edu bool predTaken; 2773794Sgblack@eecs.umich.edu 2783965Sgblack@eecs.umich.edu public: 2793965Sgblack@eecs.umich.edu 2802292SN/A#ifdef DEBUG 2812292SN/A void dumpSNList(); 2822292SN/A#endif 2832292SN/A 2842292SN/A /** Whether or not the source register is ready. 2852292SN/A * @todo: Not sure this should be here vs the derived class. 2861060SN/A */ 2871060SN/A bool _readySrcRegIdx[MaxInstSrcRegs]; 2881060SN/A 2893770Sgblack@eecs.umich.edu protected: 2903770Sgblack@eecs.umich.edu /** Flattened register index of the destination registers of this 2913770Sgblack@eecs.umich.edu * instruction. 2923770Sgblack@eecs.umich.edu */ 2933770Sgblack@eecs.umich.edu TheISA::RegIndex _flatDestRegIdx[TheISA::MaxInstDestRegs]; 2943770Sgblack@eecs.umich.edu 2953770Sgblack@eecs.umich.edu /** Flattened register index of the source registers of this 2963770Sgblack@eecs.umich.edu * instruction. 2973770Sgblack@eecs.umich.edu */ 2983770Sgblack@eecs.umich.edu TheISA::RegIndex _flatSrcRegIdx[TheISA::MaxInstSrcRegs]; 2993770Sgblack@eecs.umich.edu 3003770Sgblack@eecs.umich.edu /** Physical register index of the destination registers of this 3013770Sgblack@eecs.umich.edu * instruction. 3023770Sgblack@eecs.umich.edu */ 3033770Sgblack@eecs.umich.edu PhysRegIndex _destRegIdx[TheISA::MaxInstDestRegs]; 3043770Sgblack@eecs.umich.edu 3053770Sgblack@eecs.umich.edu /** Physical register index of the source registers of this 3063770Sgblack@eecs.umich.edu * instruction. 3073770Sgblack@eecs.umich.edu */ 3083770Sgblack@eecs.umich.edu PhysRegIndex _srcRegIdx[TheISA::MaxInstSrcRegs]; 3093770Sgblack@eecs.umich.edu 3103770Sgblack@eecs.umich.edu /** Physical register index of the previous producers of the 3113770Sgblack@eecs.umich.edu * architected destinations. 3123770Sgblack@eecs.umich.edu */ 3133770Sgblack@eecs.umich.edu PhysRegIndex _prevDestRegIdx[TheISA::MaxInstDestRegs]; 3143770Sgblack@eecs.umich.edu 3151060SN/A public: 3163770Sgblack@eecs.umich.edu 3173770Sgblack@eecs.umich.edu /** Returns the physical register index of the i'th destination 3183770Sgblack@eecs.umich.edu * register. 3193770Sgblack@eecs.umich.edu */ 3203770Sgblack@eecs.umich.edu PhysRegIndex renamedDestRegIdx(int idx) const 3213770Sgblack@eecs.umich.edu { 3223770Sgblack@eecs.umich.edu return _destRegIdx[idx]; 3233770Sgblack@eecs.umich.edu } 3243770Sgblack@eecs.umich.edu 3253770Sgblack@eecs.umich.edu /** Returns the physical register index of the i'th source register. */ 3263770Sgblack@eecs.umich.edu PhysRegIndex renamedSrcRegIdx(int idx) const 3273770Sgblack@eecs.umich.edu { 3283770Sgblack@eecs.umich.edu return _srcRegIdx[idx]; 3293770Sgblack@eecs.umich.edu } 3303770Sgblack@eecs.umich.edu 3313770Sgblack@eecs.umich.edu /** Returns the flattened register index of the i'th destination 3323770Sgblack@eecs.umich.edu * register. 3333770Sgblack@eecs.umich.edu */ 3343770Sgblack@eecs.umich.edu TheISA::RegIndex flattenedDestRegIdx(int idx) const 3353770Sgblack@eecs.umich.edu { 3363770Sgblack@eecs.umich.edu return _flatDestRegIdx[idx]; 3373770Sgblack@eecs.umich.edu } 3383770Sgblack@eecs.umich.edu 3393770Sgblack@eecs.umich.edu /** Returns the flattened register index of the i'th source register */ 3403770Sgblack@eecs.umich.edu TheISA::RegIndex flattenedSrcRegIdx(int idx) const 3413770Sgblack@eecs.umich.edu { 3423770Sgblack@eecs.umich.edu return _flatSrcRegIdx[idx]; 3433770Sgblack@eecs.umich.edu } 3443770Sgblack@eecs.umich.edu 3453770Sgblack@eecs.umich.edu /** Returns the physical register index of the previous physical register 3463770Sgblack@eecs.umich.edu * that remapped to the same logical register index. 3473770Sgblack@eecs.umich.edu */ 3483770Sgblack@eecs.umich.edu PhysRegIndex prevDestRegIdx(int idx) const 3493770Sgblack@eecs.umich.edu { 3503770Sgblack@eecs.umich.edu return _prevDestRegIdx[idx]; 3513770Sgblack@eecs.umich.edu } 3523770Sgblack@eecs.umich.edu 3533770Sgblack@eecs.umich.edu /** Renames a destination register to a physical register. Also records 3543770Sgblack@eecs.umich.edu * the previous physical register that the logical register mapped to. 3553770Sgblack@eecs.umich.edu */ 3563770Sgblack@eecs.umich.edu void renameDestReg(int idx, 3573770Sgblack@eecs.umich.edu PhysRegIndex renamed_dest, 3583770Sgblack@eecs.umich.edu PhysRegIndex previous_rename) 3593770Sgblack@eecs.umich.edu { 3603770Sgblack@eecs.umich.edu _destRegIdx[idx] = renamed_dest; 3613770Sgblack@eecs.umich.edu _prevDestRegIdx[idx] = previous_rename; 3623770Sgblack@eecs.umich.edu } 3633770Sgblack@eecs.umich.edu 3643770Sgblack@eecs.umich.edu /** Renames a source logical register to the physical register which 3653770Sgblack@eecs.umich.edu * has/will produce that logical register's result. 3663770Sgblack@eecs.umich.edu * @todo: add in whether or not the source register is ready. 3673770Sgblack@eecs.umich.edu */ 3683770Sgblack@eecs.umich.edu void renameSrcReg(int idx, PhysRegIndex renamed_src) 3693770Sgblack@eecs.umich.edu { 3703770Sgblack@eecs.umich.edu _srcRegIdx[idx] = renamed_src; 3713770Sgblack@eecs.umich.edu } 3723770Sgblack@eecs.umich.edu 3733770Sgblack@eecs.umich.edu /** Flattens a source architectural register index into a logical index. 3743770Sgblack@eecs.umich.edu */ 3753770Sgblack@eecs.umich.edu void flattenSrcReg(int idx, TheISA::RegIndex flattened_src) 3763770Sgblack@eecs.umich.edu { 3773770Sgblack@eecs.umich.edu _flatSrcRegIdx[idx] = flattened_src; 3783770Sgblack@eecs.umich.edu } 3793770Sgblack@eecs.umich.edu 3803770Sgblack@eecs.umich.edu /** Flattens a destination architectural register index into a logical 3813770Sgblack@eecs.umich.edu * index. 3823770Sgblack@eecs.umich.edu */ 3833770Sgblack@eecs.umich.edu void flattenDestReg(int idx, TheISA::RegIndex flattened_dest) 3843770Sgblack@eecs.umich.edu { 3853770Sgblack@eecs.umich.edu _flatDestRegIdx[idx] = flattened_dest; 3863770Sgblack@eecs.umich.edu } 3874636Sgblack@eecs.umich.edu /** BaseDynInst constructor given a binary instruction. 3884636Sgblack@eecs.umich.edu * @param staticInst A StaticInstPtr to the underlying instruction. 3894636Sgblack@eecs.umich.edu * @param PC The PC of the instruction. 3904636Sgblack@eecs.umich.edu * @param pred_PC The predicted next PC. 3914636Sgblack@eecs.umich.edu * @param pred_NPC The predicted next NPC. 3924636Sgblack@eecs.umich.edu * @param seq_num The sequence number of the instruction. 3934636Sgblack@eecs.umich.edu * @param cpu Pointer to the instruction's CPU. 3944636Sgblack@eecs.umich.edu */ 3954636Sgblack@eecs.umich.edu BaseDynInst(StaticInstPtr staticInst, Addr PC, Addr NPC, Addr microPC, 3964636Sgblack@eecs.umich.edu Addr pred_PC, Addr pred_NPC, Addr pred_MicroPC, 3974636Sgblack@eecs.umich.edu InstSeqNum seq_num, ImplCPU *cpu); 3983770Sgblack@eecs.umich.edu 3992292SN/A /** BaseDynInst constructor given a binary instruction. 4002292SN/A * @param inst The binary instruction. 4012292SN/A * @param PC The PC of the instruction. 4022292SN/A * @param pred_PC The predicted next PC. 4033794Sgblack@eecs.umich.edu * @param pred_NPC The predicted next NPC. 4042292SN/A * @param seq_num The sequence number of the instruction. 4052292SN/A * @param cpu Pointer to the instruction's CPU. 4062292SN/A */ 4074636Sgblack@eecs.umich.edu BaseDynInst(TheISA::ExtMachInst inst, Addr PC, Addr NPC, Addr microPC, 4084636Sgblack@eecs.umich.edu Addr pred_PC, Addr pred_NPC, Addr pred_MicroPC, 4093770Sgblack@eecs.umich.edu InstSeqNum seq_num, ImplCPU *cpu); 4101060SN/A 4112292SN/A /** BaseDynInst constructor given a StaticInst pointer. 4122292SN/A * @param _staticInst The StaticInst for this BaseDynInst. 4132292SN/A */ 4142107SN/A BaseDynInst(StaticInstPtr &_staticInst); 4151060SN/A 4161060SN/A /** BaseDynInst destructor. */ 4171060SN/A ~BaseDynInst(); 4181060SN/A 4191464SN/A private: 4201684SN/A /** Function to initialize variables in the constructors. */ 4211464SN/A void initVars(); 4221060SN/A 4231464SN/A public: 4241060SN/A /** Dumps out contents of this BaseDynInst. */ 4251060SN/A void dump(); 4261060SN/A 4271060SN/A /** Dumps out contents of this BaseDynInst into given string. */ 4281060SN/A void dump(std::string &outstring); 4291060SN/A 4303326Sktlim@umich.edu /** Read this CPU's ID. */ 4315712Shsul@eecs.umich.edu int cpuId() { return cpu->cpuId(); } 4323326Sktlim@umich.edu 4335714Shsul@eecs.umich.edu /** Read this context's system-wide ID **/ 4345714Shsul@eecs.umich.edu int contextId() { return thread->contextId(); } 4355714Shsul@eecs.umich.edu 4361060SN/A /** Returns the fault type. */ 4372132SN/A Fault getFault() { return fault; } 4381060SN/A 4391060SN/A /** Checks whether or not this instruction has had its branch target 4401060SN/A * calculated yet. For now it is not utilized and is hacked to be 4411060SN/A * always false. 4422292SN/A * @todo: Actually use this instruction. 4431060SN/A */ 4441060SN/A bool doneTargCalc() { return false; } 4451060SN/A 4461684SN/A /** Returns the next PC. This could be the speculative next PC if it is 4471684SN/A * called prior to the actual branch target being calculated. 4481684SN/A */ 4491060SN/A Addr readNextPC() { return nextPC; } 4501060SN/A 4512935Sksewell@umich.edu /** Returns the next NPC. This could be the speculative next NPC if it is 4522935Sksewell@umich.edu * called prior to the actual branch target being calculated. 4532935Sksewell@umich.edu */ 4543965Sgblack@eecs.umich.edu Addr readNextNPC() 4553965Sgblack@eecs.umich.edu { 4563965Sgblack@eecs.umich.edu#if ISA_HAS_DELAY_SLOT 4573965Sgblack@eecs.umich.edu return nextNPC; 4583965Sgblack@eecs.umich.edu#else 4593965Sgblack@eecs.umich.edu return nextPC + sizeof(TheISA::MachInst); 4603965Sgblack@eecs.umich.edu#endif 4613965Sgblack@eecs.umich.edu } 4622935Sksewell@umich.edu 4634636Sgblack@eecs.umich.edu Addr readNextMicroPC() 4644636Sgblack@eecs.umich.edu { 4654636Sgblack@eecs.umich.edu return nextMicroPC; 4664636Sgblack@eecs.umich.edu } 4674636Sgblack@eecs.umich.edu 4681060SN/A /** Set the predicted target of this current instruction. */ 4694636Sgblack@eecs.umich.edu void setPredTarg(Addr predicted_PC, Addr predicted_NPC, 4704636Sgblack@eecs.umich.edu Addr predicted_MicroPC) 4713794Sgblack@eecs.umich.edu { 4723794Sgblack@eecs.umich.edu predPC = predicted_PC; 4733794Sgblack@eecs.umich.edu predNPC = predicted_NPC; 4744636Sgblack@eecs.umich.edu predMicroPC = predicted_MicroPC; 4753794Sgblack@eecs.umich.edu } 4761060SN/A 4773794Sgblack@eecs.umich.edu /** Returns the predicted PC immediately after the branch. */ 4783794Sgblack@eecs.umich.edu Addr readPredPC() { return predPC; } 4793794Sgblack@eecs.umich.edu 4803794Sgblack@eecs.umich.edu /** Returns the predicted PC two instructions after the branch */ 4813794Sgblack@eecs.umich.edu Addr readPredNPC() { return predNPC; } 4821060SN/A 4834636Sgblack@eecs.umich.edu /** Returns the predicted micro PC after the branch */ 4844636Sgblack@eecs.umich.edu Addr readPredMicroPC() { return predMicroPC; } 4854636Sgblack@eecs.umich.edu 4861060SN/A /** Returns whether the instruction was predicted taken or not. */ 4873794Sgblack@eecs.umich.edu bool readPredTaken() 4883794Sgblack@eecs.umich.edu { 4893794Sgblack@eecs.umich.edu return predTaken; 4903794Sgblack@eecs.umich.edu } 4913794Sgblack@eecs.umich.edu 4923794Sgblack@eecs.umich.edu void setPredTaken(bool predicted_taken) 4933794Sgblack@eecs.umich.edu { 4943794Sgblack@eecs.umich.edu predTaken = predicted_taken; 4953794Sgblack@eecs.umich.edu } 4961060SN/A 4971060SN/A /** Returns whether the instruction mispredicted. */ 4982935Sksewell@umich.edu bool mispredicted() 4993794Sgblack@eecs.umich.edu { 5003965Sgblack@eecs.umich.edu return readPredPC() != readNextPC() || 5014636Sgblack@eecs.umich.edu readPredNPC() != readNextNPC() || 5024636Sgblack@eecs.umich.edu readPredMicroPC() != readNextMicroPC(); 5033794Sgblack@eecs.umich.edu } 5043794Sgblack@eecs.umich.edu 5051060SN/A // 5061060SN/A // Instruction types. Forward checks to StaticInst object. 5071060SN/A // 5085543Ssaidi@eecs.umich.edu bool isNop() const { return staticInst->isNop(); } 5095543Ssaidi@eecs.umich.edu bool isMemRef() const { return staticInst->isMemRef(); } 5105543Ssaidi@eecs.umich.edu bool isLoad() const { return staticInst->isLoad(); } 5115543Ssaidi@eecs.umich.edu bool isStore() const { return staticInst->isStore(); } 5122336SN/A bool isStoreConditional() const 5132336SN/A { return staticInst->isStoreConditional(); } 5141060SN/A bool isInstPrefetch() const { return staticInst->isInstPrefetch(); } 5151060SN/A bool isDataPrefetch() const { return staticInst->isDataPrefetch(); } 5161060SN/A bool isCopy() const { return staticInst->isCopy(); } 5175543Ssaidi@eecs.umich.edu bool isInteger() const { return staticInst->isInteger(); } 5185543Ssaidi@eecs.umich.edu bool isFloating() const { return staticInst->isFloating(); } 5195543Ssaidi@eecs.umich.edu bool isControl() const { return staticInst->isControl(); } 5205543Ssaidi@eecs.umich.edu bool isCall() const { return staticInst->isCall(); } 5215543Ssaidi@eecs.umich.edu bool isReturn() const { return staticInst->isReturn(); } 5225543Ssaidi@eecs.umich.edu bool isDirectCtrl() const { return staticInst->isDirectCtrl(); } 5231060SN/A bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); } 5245543Ssaidi@eecs.umich.edu bool isCondCtrl() const { return staticInst->isCondCtrl(); } 5255543Ssaidi@eecs.umich.edu bool isUncondCtrl() const { return staticInst->isUncondCtrl(); } 5262935Sksewell@umich.edu bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); } 5271060SN/A bool isThreadSync() const { return staticInst->isThreadSync(); } 5281060SN/A bool isSerializing() const { return staticInst->isSerializing(); } 5292292SN/A bool isSerializeBefore() const 5302731Sktlim@umich.edu { return staticInst->isSerializeBefore() || status[SerializeBefore]; } 5312292SN/A bool isSerializeAfter() const 5322731Sktlim@umich.edu { return staticInst->isSerializeAfter() || status[SerializeAfter]; } 5331060SN/A bool isMemBarrier() const { return staticInst->isMemBarrier(); } 5341060SN/A bool isWriteBarrier() const { return staticInst->isWriteBarrier(); } 5351060SN/A bool isNonSpeculative() const { return staticInst->isNonSpeculative(); } 5362292SN/A bool isQuiesce() const { return staticInst->isQuiesce(); } 5372336SN/A bool isIprAccess() const { return staticInst->isIprAccess(); } 5382308SN/A bool isUnverifiable() const { return staticInst->isUnverifiable(); } 5394828Sgblack@eecs.umich.edu bool isSyscall() const { return staticInst->isSyscall(); } 5404654Sgblack@eecs.umich.edu bool isMacroop() const { return staticInst->isMacroop(); } 5414654Sgblack@eecs.umich.edu bool isMicroop() const { return staticInst->isMicroop(); } 5424636Sgblack@eecs.umich.edu bool isDelayedCommit() const { return staticInst->isDelayedCommit(); } 5434654Sgblack@eecs.umich.edu bool isLastMicroop() const { return staticInst->isLastMicroop(); } 5444654Sgblack@eecs.umich.edu bool isFirstMicroop() const { return staticInst->isFirstMicroop(); } 5454636Sgblack@eecs.umich.edu bool isMicroBranch() const { return staticInst->isMicroBranch(); } 5462292SN/A 5472292SN/A /** Temporarily sets this instruction as a serialize before instruction. */ 5482731Sktlim@umich.edu void setSerializeBefore() { status.set(SerializeBefore); } 5492292SN/A 5502292SN/A /** Clears the serializeBefore part of this instruction. */ 5512731Sktlim@umich.edu void clearSerializeBefore() { status.reset(SerializeBefore); } 5522292SN/A 5532292SN/A /** Checks if this serializeBefore is only temporarily set. */ 5542731Sktlim@umich.edu bool isTempSerializeBefore() { return status[SerializeBefore]; } 5552292SN/A 5562292SN/A /** Temporarily sets this instruction as a serialize after instruction. */ 5572731Sktlim@umich.edu void setSerializeAfter() { status.set(SerializeAfter); } 5582292SN/A 5592292SN/A /** Clears the serializeAfter part of this instruction.*/ 5602731Sktlim@umich.edu void clearSerializeAfter() { status.reset(SerializeAfter); } 5612292SN/A 5622292SN/A /** Checks if this serializeAfter is only temporarily set. */ 5632731Sktlim@umich.edu bool isTempSerializeAfter() { return status[SerializeAfter]; } 5642292SN/A 5652731Sktlim@umich.edu /** Sets the serialization part of this instruction as handled. */ 5662731Sktlim@umich.edu void setSerializeHandled() { status.set(SerializeHandled); } 5672292SN/A 5682292SN/A /** Checks if the serialization part of this instruction has been 5692292SN/A * handled. This does not apply to the temporary serializing 5702292SN/A * state; it only applies to this instruction's own permanent 5712292SN/A * serializing state. 5722292SN/A */ 5732731Sktlim@umich.edu bool isSerializeHandled() { return status[SerializeHandled]; } 5741060SN/A 5751464SN/A /** Returns the opclass of this instruction. */ 5761464SN/A OpClass opClass() const { return staticInst->opClass(); } 5771464SN/A 5781464SN/A /** Returns the branch target address. */ 5791464SN/A Addr branchTarget() const { return staticInst->branchTarget(PC); } 5801464SN/A 5812292SN/A /** Returns the number of source registers. */ 5825543Ssaidi@eecs.umich.edu int8_t numSrcRegs() const { return staticInst->numSrcRegs(); } 5831684SN/A 5842292SN/A /** Returns the number of destination registers. */ 5851060SN/A int8_t numDestRegs() const { return staticInst->numDestRegs(); } 5861060SN/A 5871060SN/A // the following are used to track physical register usage 5881060SN/A // for machines with separate int & FP reg files 5891060SN/A int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); } 5901060SN/A int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); } 5911060SN/A 5921060SN/A /** Returns the logical register index of the i'th destination register. */ 5932292SN/A RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); } 5941060SN/A 5951060SN/A /** Returns the logical register index of the i'th source register. */ 5962292SN/A RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); } 5971060SN/A 5981684SN/A /** Returns the result of an integer instruction. */ 5991464SN/A uint64_t readIntResult() { return instResult.integer; } 6001684SN/A 6011684SN/A /** Returns the result of a floating point instruction. */ 6022356SN/A float readFloatResult() { return (float)instResult.dbl; } 6031684SN/A 6041684SN/A /** Returns the result of a floating point (double) instruction. */ 6051464SN/A double readDoubleResult() { return instResult.dbl; } 6061060SN/A 6072702Sktlim@umich.edu /** Records an integer register being set to a value. */ 6083735Sstever@eecs.umich.edu void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) 6091060SN/A { 6103326Sktlim@umich.edu if (recordResult) 6113326Sktlim@umich.edu instResult.integer = val; 6121060SN/A } 6131060SN/A 6142702Sktlim@umich.edu /** Records an fp register being set to a value. */ 6153735Sstever@eecs.umich.edu void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val, 6163735Sstever@eecs.umich.edu int width) 6172690Sktlim@umich.edu { 6183326Sktlim@umich.edu if (recordResult) { 6193326Sktlim@umich.edu if (width == 32) 6203326Sktlim@umich.edu instResult.dbl = (double)val; 6213326Sktlim@umich.edu else if (width == 64) 6223326Sktlim@umich.edu instResult.dbl = val; 6233326Sktlim@umich.edu else 6243326Sktlim@umich.edu panic("Unsupported width!"); 6253326Sktlim@umich.edu } 6262690Sktlim@umich.edu } 6272690Sktlim@umich.edu 6282702Sktlim@umich.edu /** Records an fp register being set to a value. */ 6293735Sstever@eecs.umich.edu void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 6301060SN/A { 6313326Sktlim@umich.edu if (recordResult) 6323326Sktlim@umich.edu instResult.dbl = (double)val; 6332308SN/A } 6341060SN/A 6352702Sktlim@umich.edu /** Records an fp register being set to an integer value. */ 6363735Sstever@eecs.umich.edu void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val, 6373735Sstever@eecs.umich.edu int width) 6382308SN/A { 6393326Sktlim@umich.edu if (recordResult) 6403326Sktlim@umich.edu instResult.integer = val; 6412308SN/A } 6421060SN/A 6432702Sktlim@umich.edu /** Records an fp register being set to an integer value. */ 6443735Sstever@eecs.umich.edu void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val) 6452308SN/A { 6463326Sktlim@umich.edu if (recordResult) 6473326Sktlim@umich.edu instResult.integer = val; 6481060SN/A } 6491060SN/A 6502190SN/A /** Records that one of the source registers is ready. */ 6512292SN/A void markSrcRegReady(); 6522190SN/A 6532331SN/A /** Marks a specific register as ready. */ 6542292SN/A void markSrcRegReady(RegIndex src_idx); 6552190SN/A 6561684SN/A /** Returns if a source register is ready. */ 6571464SN/A bool isReadySrcRegIdx(int idx) const 6581464SN/A { 6591464SN/A return this->_readySrcRegIdx[idx]; 6601464SN/A } 6611464SN/A 6621684SN/A /** Sets this instruction as completed. */ 6632731Sktlim@umich.edu void setCompleted() { status.set(Completed); } 6641464SN/A 6652292SN/A /** Returns whether or not this instruction is completed. */ 6662731Sktlim@umich.edu bool isCompleted() const { return status[Completed]; } 6671464SN/A 6682731Sktlim@umich.edu /** Marks the result as ready. */ 6692731Sktlim@umich.edu void setResultReady() { status.set(ResultReady); } 6702308SN/A 6712731Sktlim@umich.edu /** Returns whether or not the result is ready. */ 6722731Sktlim@umich.edu bool isResultReady() const { return status[ResultReady]; } 6732308SN/A 6741060SN/A /** Sets this instruction as ready to issue. */ 6752731Sktlim@umich.edu void setCanIssue() { status.set(CanIssue); } 6761060SN/A 6771060SN/A /** Returns whether or not this instruction is ready to issue. */ 6782731Sktlim@umich.edu bool readyToIssue() const { return status[CanIssue]; } 6791060SN/A 6804032Sktlim@umich.edu /** Clears this instruction being able to issue. */ 6814032Sktlim@umich.edu void clearCanIssue() { status.reset(CanIssue); } 6824032Sktlim@umich.edu 6831060SN/A /** Sets this instruction as issued from the IQ. */ 6842731Sktlim@umich.edu void setIssued() { status.set(Issued); } 6851060SN/A 6861060SN/A /** Returns whether or not this instruction has issued. */ 6872731Sktlim@umich.edu bool isIssued() const { return status[Issued]; } 6881060SN/A 6894032Sktlim@umich.edu /** Clears this instruction as being issued. */ 6904032Sktlim@umich.edu void clearIssued() { status.reset(Issued); } 6914032Sktlim@umich.edu 6921060SN/A /** Sets this instruction as executed. */ 6932731Sktlim@umich.edu void setExecuted() { status.set(Executed); } 6941060SN/A 6951060SN/A /** Returns whether or not this instruction has executed. */ 6962731Sktlim@umich.edu bool isExecuted() const { return status[Executed]; } 6971060SN/A 6981060SN/A /** Sets this instruction as ready to commit. */ 6992731Sktlim@umich.edu void setCanCommit() { status.set(CanCommit); } 7001060SN/A 7011061SN/A /** Clears this instruction as being ready to commit. */ 7022731Sktlim@umich.edu void clearCanCommit() { status.reset(CanCommit); } 7031061SN/A 7041060SN/A /** Returns whether or not this instruction is ready to commit. */ 7052731Sktlim@umich.edu bool readyToCommit() const { return status[CanCommit]; } 7062731Sktlim@umich.edu 7072731Sktlim@umich.edu void setAtCommit() { status.set(AtCommit); } 7082731Sktlim@umich.edu 7092731Sktlim@umich.edu bool isAtCommit() { return status[AtCommit]; } 7101060SN/A 7112292SN/A /** Sets this instruction as committed. */ 7122731Sktlim@umich.edu void setCommitted() { status.set(Committed); } 7132292SN/A 7142292SN/A /** Returns whether or not this instruction is committed. */ 7152731Sktlim@umich.edu bool isCommitted() const { return status[Committed]; } 7162292SN/A 7171060SN/A /** Sets this instruction as squashed. */ 7182731Sktlim@umich.edu void setSquashed() { status.set(Squashed); } 7191060SN/A 7201060SN/A /** Returns whether or not this instruction is squashed. */ 7212731Sktlim@umich.edu bool isSquashed() const { return status[Squashed]; } 7221060SN/A 7232292SN/A //Instruction Queue Entry 7242292SN/A //----------------------- 7252292SN/A /** Sets this instruction as a entry the IQ. */ 7262731Sktlim@umich.edu void setInIQ() { status.set(IqEntry); } 7272292SN/A 7282292SN/A /** Sets this instruction as a entry the IQ. */ 7292731Sktlim@umich.edu void clearInIQ() { status.reset(IqEntry); } 7302731Sktlim@umich.edu 7312731Sktlim@umich.edu /** Returns whether or not this instruction has issued. */ 7322731Sktlim@umich.edu bool isInIQ() const { return status[IqEntry]; } 7332292SN/A 7341060SN/A /** Sets this instruction as squashed in the IQ. */ 7352731Sktlim@umich.edu void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);} 7361060SN/A 7371060SN/A /** Returns whether or not this instruction is squashed in the IQ. */ 7382731Sktlim@umich.edu bool isSquashedInIQ() const { return status[SquashedInIQ]; } 7392292SN/A 7402292SN/A 7412292SN/A //Load / Store Queue Functions 7422292SN/A //----------------------- 7432292SN/A /** Sets this instruction as a entry the LSQ. */ 7442731Sktlim@umich.edu void setInLSQ() { status.set(LsqEntry); } 7452292SN/A 7462292SN/A /** Sets this instruction as a entry the LSQ. */ 7472731Sktlim@umich.edu void removeInLSQ() { status.reset(LsqEntry); } 7482731Sktlim@umich.edu 7492731Sktlim@umich.edu /** Returns whether or not this instruction is in the LSQ. */ 7502731Sktlim@umich.edu bool isInLSQ() const { return status[LsqEntry]; } 7512292SN/A 7522292SN/A /** Sets this instruction as squashed in the LSQ. */ 7532731Sktlim@umich.edu void setSquashedInLSQ() { status.set(SquashedInLSQ);} 7542292SN/A 7552292SN/A /** Returns whether or not this instruction is squashed in the LSQ. */ 7562731Sktlim@umich.edu bool isSquashedInLSQ() const { return status[SquashedInLSQ]; } 7572292SN/A 7582292SN/A 7592292SN/A //Reorder Buffer Functions 7602292SN/A //----------------------- 7612292SN/A /** Sets this instruction as a entry the ROB. */ 7622731Sktlim@umich.edu void setInROB() { status.set(RobEntry); } 7632292SN/A 7642292SN/A /** Sets this instruction as a entry the ROB. */ 7652731Sktlim@umich.edu void clearInROB() { status.reset(RobEntry); } 7662731Sktlim@umich.edu 7672731Sktlim@umich.edu /** Returns whether or not this instruction is in the ROB. */ 7682731Sktlim@umich.edu bool isInROB() const { return status[RobEntry]; } 7692292SN/A 7702292SN/A /** Sets this instruction as squashed in the ROB. */ 7712731Sktlim@umich.edu void setSquashedInROB() { status.set(SquashedInROB); } 7722292SN/A 7732292SN/A /** Returns whether or not this instruction is squashed in the ROB. */ 7742731Sktlim@umich.edu bool isSquashedInROB() const { return status[SquashedInROB]; } 7752292SN/A 7761060SN/A /** Read the PC of this instruction. */ 7771464SN/A const Addr readPC() const { return PC; } 7781060SN/A 7794636Sgblack@eecs.umich.edu /**Read the micro PC of this instruction. */ 7804636Sgblack@eecs.umich.edu const Addr readMicroPC() const { return microPC; } 7814636Sgblack@eecs.umich.edu 7821060SN/A /** Set the next PC of this instruction (its actual target). */ 7834636Sgblack@eecs.umich.edu void setNextPC(Addr val) 7842308SN/A { 7852308SN/A nextPC = val; 7862308SN/A } 7872190SN/A 7882935Sksewell@umich.edu /** Set the next NPC of this instruction (the target in Mips or Sparc).*/ 7894636Sgblack@eecs.umich.edu void setNextNPC(Addr val) 7902935Sksewell@umich.edu { 7914632Sgblack@eecs.umich.edu#if ISA_HAS_DELAY_SLOT 7922935Sksewell@umich.edu nextNPC = val; 7934632Sgblack@eecs.umich.edu#endif 7942935Sksewell@umich.edu } 7952935Sksewell@umich.edu 7964636Sgblack@eecs.umich.edu void setNextMicroPC(Addr val) 7974636Sgblack@eecs.umich.edu { 7984636Sgblack@eecs.umich.edu nextMicroPC = val; 7994636Sgblack@eecs.umich.edu } 8004636Sgblack@eecs.umich.edu 8017597Sminkyu.jeong@arm.com bool readPredicate() 8027597Sminkyu.jeong@arm.com { 8037597Sminkyu.jeong@arm.com return predicate; 8047597Sminkyu.jeong@arm.com } 8057597Sminkyu.jeong@arm.com 8067597Sminkyu.jeong@arm.com void setPredicate(bool val) 8077597Sminkyu.jeong@arm.com { 8087597Sminkyu.jeong@arm.com predicate = val; 8097600Sminkyu.jeong@arm.com 8107600Sminkyu.jeong@arm.com if (traceData) { 8117600Sminkyu.jeong@arm.com traceData->setPredicate(val); 8127600Sminkyu.jeong@arm.com } 8137597Sminkyu.jeong@arm.com } 8147597Sminkyu.jeong@arm.com 8152702Sktlim@umich.edu /** Sets the ASID. */ 8162292SN/A void setASID(short addr_space_id) { asid = addr_space_id; } 8172292SN/A 8182702Sktlim@umich.edu /** Sets the thread id. */ 8196221Snate@binkert.org void setTid(ThreadID tid) { threadNumber = tid; } 8202292SN/A 8212731Sktlim@umich.edu /** Sets the pointer to the thread state. */ 8222702Sktlim@umich.edu void setThreadState(ImplState *state) { thread = state; } 8231060SN/A 8242731Sktlim@umich.edu /** Returns the thread context. */ 8252680Sktlim@umich.edu ThreadContext *tcBase() { return thread->getTC(); } 8261464SN/A 8271464SN/A private: 8281684SN/A /** Instruction effective address. 8291684SN/A * @todo: Consider if this is necessary or not. 8301684SN/A */ 8311464SN/A Addr instEffAddr; 8322292SN/A 8331684SN/A /** Whether or not the effective address calculation is completed. 8341684SN/A * @todo: Consider if this is necessary or not. 8351684SN/A */ 8361464SN/A bool eaCalcDone; 8371464SN/A 8384032Sktlim@umich.edu /** Is this instruction's memory access uncacheable. */ 8394032Sktlim@umich.edu bool isUncacheable; 8404032Sktlim@umich.edu 8414032Sktlim@umich.edu /** Has this instruction generated a memory request. */ 8424032Sktlim@umich.edu bool reqMade; 8434032Sktlim@umich.edu 8441464SN/A public: 8451684SN/A /** Sets the effective address. */ 8461464SN/A void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; } 8471684SN/A 8481684SN/A /** Returns the effective address. */ 8491464SN/A const Addr &getEA() const { return instEffAddr; } 8501684SN/A 8511684SN/A /** Returns whether or not the eff. addr. calculation has been completed. */ 8521464SN/A bool doneEACalc() { return eaCalcDone; } 8531684SN/A 8541684SN/A /** Returns whether or not the eff. addr. source registers are ready. */ 8551464SN/A bool eaSrcsReady(); 8561681SN/A 8572292SN/A /** Whether or not the memory operation is done. */ 8582292SN/A bool memOpDone; 8592292SN/A 8604032Sktlim@umich.edu /** Is this instruction's memory access uncacheable. */ 8614032Sktlim@umich.edu bool uncacheable() { return isUncacheable; } 8624032Sktlim@umich.edu 8634032Sktlim@umich.edu /** Has this instruction generated a memory request. */ 8644032Sktlim@umich.edu bool hasRequest() { return reqMade; } 8654032Sktlim@umich.edu 8661681SN/A public: 8671684SN/A /** Load queue index. */ 8681681SN/A int16_t lqIdx; 8691684SN/A 8701684SN/A /** Store queue index. */ 8711681SN/A int16_t sqIdx; 8722292SN/A 8732292SN/A /** Iterator pointing to this BaseDynInst in the list of all insts. */ 8742292SN/A ListIt instListIt; 8752292SN/A 8762292SN/A /** Returns iterator to this instruction in the list of all insts. */ 8772292SN/A ListIt &getInstListIt() { return instListIt; } 8782292SN/A 8792292SN/A /** Sets iterator for this instruction in the list of all insts. */ 8802292SN/A void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; } 8813326Sktlim@umich.edu 8823326Sktlim@umich.edu public: 8833326Sktlim@umich.edu /** Returns the number of consecutive store conditional failures. */ 8843326Sktlim@umich.edu unsigned readStCondFailures() 8853326Sktlim@umich.edu { return thread->storeCondFailures; } 8863326Sktlim@umich.edu 8873326Sktlim@umich.edu /** Sets the number of consecutive store conditional failures. */ 8883326Sktlim@umich.edu void setStCondFailures(unsigned sc_failures) 8893326Sktlim@umich.edu { thread->storeCondFailures = sc_failures; } 8901060SN/A}; 8911060SN/A 8921060SN/Atemplate<class Impl> 8937520Sgblack@eecs.umich.eduFault 8947520Sgblack@eecs.umich.eduBaseDynInst<Impl>::readBytes(Addr addr, uint8_t *data, 8957520Sgblack@eecs.umich.edu unsigned size, unsigned flags) 8961060SN/A{ 8974032Sktlim@umich.edu reqMade = true; 8987520Sgblack@eecs.umich.edu Request *req = new Request(asid, addr, size, flags, this->PC, 8996429Ssteve.reinhardt@amd.com thread->contextId(), threadNumber); 9002292SN/A 9016974Stjones1@inf.ed.ac.uk Request *sreqLow = NULL; 9026974Stjones1@inf.ed.ac.uk Request *sreqHigh = NULL; 9036974Stjones1@inf.ed.ac.uk 9046974Stjones1@inf.ed.ac.uk // Only split the request if the ISA supports unaligned accesses. 9056974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc) { 9066974Stjones1@inf.ed.ac.uk splitRequest(req, sreqLow, sreqHigh); 9076974Stjones1@inf.ed.ac.uk } 9086974Stjones1@inf.ed.ac.uk initiateTranslation(req, sreqLow, sreqHigh, NULL, BaseTLB::Read); 9094032Sktlim@umich.edu 9102678Sktlim@umich.edu if (fault == NoFault) { 9112678Sktlim@umich.edu effAddr = req->getVaddr(); 9124032Sktlim@umich.edu effAddrValid = true; 9136975Stjones1@inf.ed.ac.uk fault = cpu->read(req, sreqLow, sreqHigh, data, lqIdx); 9146973Stjones1@inf.ed.ac.uk } else { 9152292SN/A // Commit will have to clean up whatever happened. Set this 9162292SN/A // instruction as executed. 9172292SN/A this->setExecuted(); 9181060SN/A } 9191060SN/A 9207577SAli.Saidi@ARM.com if (fault != NoFault) { 9217577SAli.Saidi@ARM.com // Return a fixed value to keep simulation deterministic even 9227577SAli.Saidi@ARM.com // along misspeculated paths. 9237577SAli.Saidi@ARM.com bzero(data, size); 9247577SAli.Saidi@ARM.com } 9257577SAli.Saidi@ARM.com 9261060SN/A if (traceData) { 9271060SN/A traceData->setAddr(addr); 9281060SN/A } 9291060SN/A 9301060SN/A return fault; 9311060SN/A} 9321060SN/A 9331060SN/Atemplate<class Impl> 9341060SN/Atemplate<class T> 9352132SN/Ainline Fault 9367520Sgblack@eecs.umich.eduBaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags) 9377520Sgblack@eecs.umich.edu{ 9387520Sgblack@eecs.umich.edu Fault fault = readBytes(addr, (uint8_t *)&data, sizeof(T), flags); 9397520Sgblack@eecs.umich.edu 9407520Sgblack@eecs.umich.edu data = TheISA::gtoh(data); 9417520Sgblack@eecs.umich.edu 9427520Sgblack@eecs.umich.edu if (traceData) { 9437520Sgblack@eecs.umich.edu traceData->setData(data); 9447520Sgblack@eecs.umich.edu } 9457520Sgblack@eecs.umich.edu 9467520Sgblack@eecs.umich.edu return fault; 9477520Sgblack@eecs.umich.edu} 9487520Sgblack@eecs.umich.edu 9497520Sgblack@eecs.umich.edutemplate<class Impl> 9507520Sgblack@eecs.umich.eduFault 9517520Sgblack@eecs.umich.eduBaseDynInst<Impl>::writeBytes(uint8_t *data, unsigned size, 9527520Sgblack@eecs.umich.edu Addr addr, unsigned flags, uint64_t *res) 9531060SN/A{ 9541060SN/A if (traceData) { 9551060SN/A traceData->setAddr(addr); 9561060SN/A } 9571060SN/A 9584032Sktlim@umich.edu reqMade = true; 9597520Sgblack@eecs.umich.edu Request *req = new Request(asid, addr, size, flags, this->PC, 9606429Ssteve.reinhardt@amd.com thread->contextId(), threadNumber); 9611060SN/A 9626974Stjones1@inf.ed.ac.uk Request *sreqLow = NULL; 9636974Stjones1@inf.ed.ac.uk Request *sreqHigh = NULL; 9646974Stjones1@inf.ed.ac.uk 9656974Stjones1@inf.ed.ac.uk // Only split the request if the ISA supports unaligned accesses. 9666974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc) { 9676974Stjones1@inf.ed.ac.uk splitRequest(req, sreqLow, sreqHigh); 9686974Stjones1@inf.ed.ac.uk } 9696974Stjones1@inf.ed.ac.uk initiateTranslation(req, sreqLow, sreqHigh, res, BaseTLB::Write); 9704032Sktlim@umich.edu 9712090SN/A if (fault == NoFault) { 9722678Sktlim@umich.edu effAddr = req->getVaddr(); 9734032Sktlim@umich.edu effAddrValid = true; 9746975Stjones1@inf.ed.ac.uk fault = cpu->write(req, sreqLow, sreqHigh, data, sqIdx); 9751060SN/A } 9761060SN/A 9771060SN/A return fault; 9781060SN/A} 9791060SN/A 9806973Stjones1@inf.ed.ac.uktemplate<class Impl> 9817520Sgblack@eecs.umich.edutemplate<class T> 9827520Sgblack@eecs.umich.eduinline Fault 9837520Sgblack@eecs.umich.eduBaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res) 9847520Sgblack@eecs.umich.edu{ 9857520Sgblack@eecs.umich.edu if (traceData) { 9867520Sgblack@eecs.umich.edu traceData->setData(data); 9877520Sgblack@eecs.umich.edu } 9887520Sgblack@eecs.umich.edu data = TheISA::htog(data); 9897520Sgblack@eecs.umich.edu return writeBytes((uint8_t *)&data, sizeof(T), addr, flags, res); 9907520Sgblack@eecs.umich.edu} 9917520Sgblack@eecs.umich.edu 9927520Sgblack@eecs.umich.edutemplate<class Impl> 9936973Stjones1@inf.ed.ac.ukinline void 9946974Stjones1@inf.ed.ac.ukBaseDynInst<Impl>::splitRequest(RequestPtr req, RequestPtr &sreqLow, 9956974Stjones1@inf.ed.ac.uk RequestPtr &sreqHigh) 9966974Stjones1@inf.ed.ac.uk{ 9976974Stjones1@inf.ed.ac.uk // Check to see if the request crosses the next level block boundary. 9986974Stjones1@inf.ed.ac.uk unsigned block_size = cpu->getDcachePort()->peerBlockSize(); 9996974Stjones1@inf.ed.ac.uk Addr addr = req->getVaddr(); 10006974Stjones1@inf.ed.ac.uk Addr split_addr = roundDown(addr + req->getSize() - 1, block_size); 10016974Stjones1@inf.ed.ac.uk assert(split_addr <= addr || split_addr - addr < block_size); 10026974Stjones1@inf.ed.ac.uk 10036974Stjones1@inf.ed.ac.uk // Spans two blocks. 10046974Stjones1@inf.ed.ac.uk if (split_addr > addr) { 10056974Stjones1@inf.ed.ac.uk req->splitOnVaddr(split_addr, sreqLow, sreqHigh); 10066974Stjones1@inf.ed.ac.uk } 10076974Stjones1@inf.ed.ac.uk} 10086974Stjones1@inf.ed.ac.uk 10096974Stjones1@inf.ed.ac.uktemplate<class Impl> 10106974Stjones1@inf.ed.ac.ukinline void 10116974Stjones1@inf.ed.ac.ukBaseDynInst<Impl>::initiateTranslation(RequestPtr req, RequestPtr sreqLow, 10126974Stjones1@inf.ed.ac.uk RequestPtr sreqHigh, uint64_t *res, 10136973Stjones1@inf.ed.ac.uk BaseTLB::Mode mode) 10146973Stjones1@inf.ed.ac.uk{ 10156974Stjones1@inf.ed.ac.uk if (!TheISA::HasUnalignedMemAcc || sreqLow == NULL) { 10166974Stjones1@inf.ed.ac.uk WholeTranslationState *state = 10176974Stjones1@inf.ed.ac.uk new WholeTranslationState(req, NULL, res, mode); 10186974Stjones1@inf.ed.ac.uk 10196974Stjones1@inf.ed.ac.uk // One translation if the request isn't split. 10206974Stjones1@inf.ed.ac.uk DataTranslation<BaseDynInst<Impl> > *trans = 10216974Stjones1@inf.ed.ac.uk new DataTranslation<BaseDynInst<Impl> >(this, state); 10226974Stjones1@inf.ed.ac.uk cpu->dtb->translateTiming(req, thread->getTC(), trans, mode); 10236974Stjones1@inf.ed.ac.uk } else { 10246974Stjones1@inf.ed.ac.uk WholeTranslationState *state = 10256974Stjones1@inf.ed.ac.uk new WholeTranslationState(req, sreqLow, sreqHigh, NULL, res, mode); 10266974Stjones1@inf.ed.ac.uk 10276974Stjones1@inf.ed.ac.uk // Two translations when the request is split. 10286974Stjones1@inf.ed.ac.uk DataTranslation<BaseDynInst<Impl> > *stransLow = 10296974Stjones1@inf.ed.ac.uk new DataTranslation<BaseDynInst<Impl> >(this, state, 0); 10306974Stjones1@inf.ed.ac.uk DataTranslation<BaseDynInst<Impl> > *stransHigh = 10316974Stjones1@inf.ed.ac.uk new DataTranslation<BaseDynInst<Impl> >(this, state, 1); 10326974Stjones1@inf.ed.ac.uk 10336974Stjones1@inf.ed.ac.uk cpu->dtb->translateTiming(sreqLow, thread->getTC(), stransLow, mode); 10346974Stjones1@inf.ed.ac.uk cpu->dtb->translateTiming(sreqHigh, thread->getTC(), stransHigh, mode); 10356974Stjones1@inf.ed.ac.uk } 10366973Stjones1@inf.ed.ac.uk} 10376973Stjones1@inf.ed.ac.uk 10386973Stjones1@inf.ed.ac.uktemplate<class Impl> 10396973Stjones1@inf.ed.ac.ukinline void 10406973Stjones1@inf.ed.ac.ukBaseDynInst<Impl>::finishTranslation(WholeTranslationState *state) 10416973Stjones1@inf.ed.ac.uk{ 10426973Stjones1@inf.ed.ac.uk fault = state->getFault(); 10436973Stjones1@inf.ed.ac.uk 10446973Stjones1@inf.ed.ac.uk if (state->isUncacheable()) 10456973Stjones1@inf.ed.ac.uk isUncacheable = true; 10466973Stjones1@inf.ed.ac.uk 10476973Stjones1@inf.ed.ac.uk if (fault == NoFault) { 10486973Stjones1@inf.ed.ac.uk physEffAddr = state->getPaddr(); 10496973Stjones1@inf.ed.ac.uk memReqFlags = state->getFlags(); 10506973Stjones1@inf.ed.ac.uk 10516973Stjones1@inf.ed.ac.uk if (state->mainReq->isCondSwap()) { 10526973Stjones1@inf.ed.ac.uk assert(state->res); 10536973Stjones1@inf.ed.ac.uk state->mainReq->setExtraData(*state->res); 10546973Stjones1@inf.ed.ac.uk } 10556973Stjones1@inf.ed.ac.uk 10566973Stjones1@inf.ed.ac.uk } else { 10576973Stjones1@inf.ed.ac.uk state->deleteReqs(); 10586973Stjones1@inf.ed.ac.uk } 10596973Stjones1@inf.ed.ac.uk delete state; 10606973Stjones1@inf.ed.ac.uk} 10616973Stjones1@inf.ed.ac.uk 10621464SN/A#endif // __CPU_BASE_DYN_INST_HH__ 1063