base_dyn_inst.hh revision 7678
1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * Copyright (c) 2009 The University of Edinburgh 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer; 10 * redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution; 13 * neither the name of the copyright holders nor the names of its 14 * contributors may be used to endorse or promote products derived from 15 * this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * Authors: Kevin Lim 30 * Timothy M. Jones 31 */ 32 33#ifndef __CPU_BASE_DYN_INST_HH__ 34#define __CPU_BASE_DYN_INST_HH__ 35 36#include <bitset> 37#include <list> 38#include <string> 39 40#include "arch/faults.hh" 41#include "base/fast_alloc.hh" 42#include "base/trace.hh" 43#include "config/full_system.hh" 44#include "config/the_isa.hh" 45#include "cpu/o3/comm.hh" 46#include "cpu/exetrace.hh" 47#include "cpu/inst_seq.hh" 48#include "cpu/op_class.hh" 49#include "cpu/static_inst.hh" 50#include "cpu/translation.hh" 51#include "mem/packet.hh" 52#include "sim/byteswap.hh" 53#include "sim/system.hh" 54#include "sim/tlb.hh" 55 56/** 57 * @file 58 * Defines a dynamic instruction context. 59 */ 60 61// Forward declaration. 62class StaticInstPtr; 63 64template <class Impl> 65class BaseDynInst : public FastAlloc, public RefCounted 66{ 67 public: 68 // Typedef for the CPU. 69 typedef typename Impl::CPUType ImplCPU; 70 typedef typename ImplCPU::ImplState ImplState; 71 72 // Logical register index type. 73 typedef TheISA::RegIndex RegIndex; 74 // Integer register type. 75 typedef TheISA::IntReg IntReg; 76 // Floating point register type. 77 typedef TheISA::FloatReg FloatReg; 78 79 // The DynInstPtr type. 80 typedef typename Impl::DynInstPtr DynInstPtr; 81 82 // The list of instructions iterator type. 83 typedef typename std::list<DynInstPtr>::iterator ListIt; 84 85 enum { 86 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs 87 MaxInstDestRegs = TheISA::MaxInstDestRegs, /// Max dest regs 88 }; 89 90 /** The StaticInst used by this BaseDynInst. */ 91 StaticInstPtr staticInst; 92 93 //////////////////////////////////////////// 94 // 95 // INSTRUCTION EXECUTION 96 // 97 //////////////////////////////////////////// 98 /** InstRecord that tracks this instructions. */ 99 Trace::InstRecord *traceData; 100 101 void demapPage(Addr vaddr, uint64_t asn) 102 { 103 cpu->demapPage(vaddr, asn); 104 } 105 void demapInstPage(Addr vaddr, uint64_t asn) 106 { 107 cpu->demapPage(vaddr, asn); 108 } 109 void demapDataPage(Addr vaddr, uint64_t asn) 110 { 111 cpu->demapPage(vaddr, asn); 112 } 113 114 /** 115 * Does a read to a given address. 116 * @param addr The address to read. 117 * @param data The read's data is written into this parameter. 118 * @param flags The request's flags. 119 * @return Returns any fault due to the read. 120 */ 121 template <class T> 122 Fault read(Addr addr, T &data, unsigned flags); 123 124 Fault readBytes(Addr addr, uint8_t *data, unsigned size, unsigned flags); 125 126 /** 127 * Does a write to a given address. 128 * @param data The data to be written. 129 * @param addr The address to write to. 130 * @param flags The request's flags. 131 * @param res The result of the write (for load locked/store conditionals). 132 * @return Returns any fault due to the write. 133 */ 134 template <class T> 135 Fault write(T data, Addr addr, unsigned flags, uint64_t *res); 136 137 Fault writeBytes(uint8_t *data, unsigned size, 138 Addr addr, unsigned flags, uint64_t *res); 139 140 /** Splits a request in two if it crosses a dcache block. */ 141 void splitRequest(RequestPtr req, RequestPtr &sreqLow, 142 RequestPtr &sreqHigh); 143 144 /** Initiate a DTB address translation. */ 145 void initiateTranslation(RequestPtr req, RequestPtr sreqLow, 146 RequestPtr sreqHigh, uint64_t *res, 147 BaseTLB::Mode mode); 148 149 /** Finish a DTB address translation. */ 150 void finishTranslation(WholeTranslationState *state); 151 152 void prefetch(Addr addr, unsigned flags); 153 void writeHint(Addr addr, int size, unsigned flags); 154 Fault copySrcTranslate(Addr src); 155 Fault copy(Addr dest); 156 157 /** @todo: Consider making this private. */ 158 public: 159 /** The sequence number of the instruction. */ 160 InstSeqNum seqNum; 161 162 enum Status { 163 IqEntry, /// Instruction is in the IQ 164 RobEntry, /// Instruction is in the ROB 165 LsqEntry, /// Instruction is in the LSQ 166 Completed, /// Instruction has completed 167 ResultReady, /// Instruction has its result 168 CanIssue, /// Instruction can issue and execute 169 Issued, /// Instruction has issued 170 Executed, /// Instruction has executed 171 CanCommit, /// Instruction can commit 172 AtCommit, /// Instruction has reached commit 173 Committed, /// Instruction has committed 174 Squashed, /// Instruction is squashed 175 SquashedInIQ, /// Instruction is squashed in the IQ 176 SquashedInLSQ, /// Instruction is squashed in the LSQ 177 SquashedInROB, /// Instruction is squashed in the ROB 178 RecoverInst, /// Is a recover instruction 179 BlockingInst, /// Is a blocking instruction 180 ThreadsyncWait, /// Is a thread synchronization instruction 181 SerializeBefore, /// Needs to serialize on 182 /// instructions ahead of it 183 SerializeAfter, /// Needs to serialize instructions behind it 184 SerializeHandled, /// Serialization has been handled 185 NumStatus 186 }; 187 188 /** The status of this BaseDynInst. Several bits can be set. */ 189 std::bitset<NumStatus> status; 190 191 /** The thread this instruction is from. */ 192 ThreadID threadNumber; 193 194 /** data address space ID, for loads & stores. */ 195 short asid; 196 197 /** How many source registers are ready. */ 198 unsigned readyRegs; 199 200 /** Pointer to the Impl's CPU object. */ 201 ImplCPU *cpu; 202 203 /** Pointer to the thread state. */ 204 ImplState *thread; 205 206 /** The kind of fault this instruction has generated. */ 207 Fault fault; 208 209 /** Pointer to the data for the memory access. */ 210 uint8_t *memData; 211 212 /** The effective virtual address (lds & stores only). */ 213 Addr effAddr; 214 215 /** Is the effective virtual address valid. */ 216 bool effAddrValid; 217 218 /** The effective physical address. */ 219 Addr physEffAddr; 220 221 /** Effective virtual address for a copy source. */ 222 Addr copySrcEffAddr; 223 224 /** Effective physical address for a copy source. */ 225 Addr copySrcPhysEffAddr; 226 227 /** The memory request flags (from translation). */ 228 unsigned memReqFlags; 229 230 union Result { 231 uint64_t integer; 232// float fp; 233 double dbl; 234 }; 235 236 /** The result of the instruction; assumes for now that there's only one 237 * destination register. 238 */ 239 Result instResult; 240 241 /** Records changes to result? */ 242 bool recordResult; 243 244 /** PC of this instruction. */ 245 Addr PC; 246 247 /** Micro PC of this instruction. */ 248 Addr microPC; 249 250 /** Did this instruction execute, or is it predicated false */ 251 bool predicate; 252 253 protected: 254 /** Next non-speculative PC. It is not filled in at fetch, but rather 255 * once the target of the branch is truly known (either decode or 256 * execute). 257 */ 258 Addr nextPC; 259 260 /** Next non-speculative NPC. Target PC for Mips or Sparc. */ 261 Addr nextNPC; 262 263 /** Next non-speculative micro PC. */ 264 Addr nextMicroPC; 265 266 /** Predicted next PC. */ 267 Addr predPC; 268 269 /** Predicted next NPC. */ 270 Addr predNPC; 271 272 /** Predicted next microPC */ 273 Addr predMicroPC; 274 275 /** If this is a branch that was predicted taken */ 276 bool predTaken; 277 278 public: 279 280#ifdef DEBUG 281 void dumpSNList(); 282#endif 283 284 /** Whether or not the source register is ready. 285 * @todo: Not sure this should be here vs the derived class. 286 */ 287 bool _readySrcRegIdx[MaxInstSrcRegs]; 288 289 protected: 290 /** Flattened register index of the destination registers of this 291 * instruction. 292 */ 293 TheISA::RegIndex _flatDestRegIdx[TheISA::MaxInstDestRegs]; 294 295 /** Flattened register index of the source registers of this 296 * instruction. 297 */ 298 TheISA::RegIndex _flatSrcRegIdx[TheISA::MaxInstSrcRegs]; 299 300 /** Physical register index of the destination registers of this 301 * instruction. 302 */ 303 PhysRegIndex _destRegIdx[TheISA::MaxInstDestRegs]; 304 305 /** Physical register index of the source registers of this 306 * instruction. 307 */ 308 PhysRegIndex _srcRegIdx[TheISA::MaxInstSrcRegs]; 309 310 /** Physical register index of the previous producers of the 311 * architected destinations. 312 */ 313 PhysRegIndex _prevDestRegIdx[TheISA::MaxInstDestRegs]; 314 315 public: 316 317 /** Returns the physical register index of the i'th destination 318 * register. 319 */ 320 PhysRegIndex renamedDestRegIdx(int idx) const 321 { 322 return _destRegIdx[idx]; 323 } 324 325 /** Returns the physical register index of the i'th source register. */ 326 PhysRegIndex renamedSrcRegIdx(int idx) const 327 { 328 return _srcRegIdx[idx]; 329 } 330 331 /** Returns the flattened register index of the i'th destination 332 * register. 333 */ 334 TheISA::RegIndex flattenedDestRegIdx(int idx) const 335 { 336 return _flatDestRegIdx[idx]; 337 } 338 339 /** Returns the flattened register index of the i'th source register */ 340 TheISA::RegIndex flattenedSrcRegIdx(int idx) const 341 { 342 return _flatSrcRegIdx[idx]; 343 } 344 345 /** Returns the physical register index of the previous physical register 346 * that remapped to the same logical register index. 347 */ 348 PhysRegIndex prevDestRegIdx(int idx) const 349 { 350 return _prevDestRegIdx[idx]; 351 } 352 353 /** Renames a destination register to a physical register. Also records 354 * the previous physical register that the logical register mapped to. 355 */ 356 void renameDestReg(int idx, 357 PhysRegIndex renamed_dest, 358 PhysRegIndex previous_rename) 359 { 360 _destRegIdx[idx] = renamed_dest; 361 _prevDestRegIdx[idx] = previous_rename; 362 } 363 364 /** Renames a source logical register to the physical register which 365 * has/will produce that logical register's result. 366 * @todo: add in whether or not the source register is ready. 367 */ 368 void renameSrcReg(int idx, PhysRegIndex renamed_src) 369 { 370 _srcRegIdx[idx] = renamed_src; 371 } 372 373 /** Flattens a source architectural register index into a logical index. 374 */ 375 void flattenSrcReg(int idx, TheISA::RegIndex flattened_src) 376 { 377 _flatSrcRegIdx[idx] = flattened_src; 378 } 379 380 /** Flattens a destination architectural register index into a logical 381 * index. 382 */ 383 void flattenDestReg(int idx, TheISA::RegIndex flattened_dest) 384 { 385 _flatDestRegIdx[idx] = flattened_dest; 386 } 387 /** BaseDynInst constructor given a binary instruction. 388 * @param staticInst A StaticInstPtr to the underlying instruction. 389 * @param PC The PC of the instruction. 390 * @param pred_PC The predicted next PC. 391 * @param pred_NPC The predicted next NPC. 392 * @param seq_num The sequence number of the instruction. 393 * @param cpu Pointer to the instruction's CPU. 394 */ 395 BaseDynInst(StaticInstPtr staticInst, Addr PC, Addr NPC, Addr microPC, 396 Addr pred_PC, Addr pred_NPC, Addr pred_MicroPC, 397 InstSeqNum seq_num, ImplCPU *cpu); 398 399 /** BaseDynInst constructor given a binary instruction. 400 * @param inst The binary instruction. 401 * @param PC The PC of the instruction. 402 * @param pred_PC The predicted next PC. 403 * @param pred_NPC The predicted next NPC. 404 * @param seq_num The sequence number of the instruction. 405 * @param cpu Pointer to the instruction's CPU. 406 */ 407 BaseDynInst(TheISA::ExtMachInst inst, Addr PC, Addr NPC, Addr microPC, 408 Addr pred_PC, Addr pred_NPC, Addr pred_MicroPC, 409 InstSeqNum seq_num, ImplCPU *cpu); 410 411 /** BaseDynInst constructor given a StaticInst pointer. 412 * @param _staticInst The StaticInst for this BaseDynInst. 413 */ 414 BaseDynInst(StaticInstPtr &_staticInst); 415 416 /** BaseDynInst destructor. */ 417 ~BaseDynInst(); 418 419 private: 420 /** Function to initialize variables in the constructors. */ 421 void initVars(); 422 423 public: 424 /** Dumps out contents of this BaseDynInst. */ 425 void dump(); 426 427 /** Dumps out contents of this BaseDynInst into given string. */ 428 void dump(std::string &outstring); 429 430 /** Read this CPU's ID. */ 431 int cpuId() { return cpu->cpuId(); } 432 433 /** Read this context's system-wide ID **/ 434 int contextId() { return thread->contextId(); } 435 436 /** Returns the fault type. */ 437 Fault getFault() { return fault; } 438 439 /** Checks whether or not this instruction has had its branch target 440 * calculated yet. For now it is not utilized and is hacked to be 441 * always false. 442 * @todo: Actually use this instruction. 443 */ 444 bool doneTargCalc() { return false; } 445 446 /** Returns the next PC. This could be the speculative next PC if it is 447 * called prior to the actual branch target being calculated. 448 */ 449 Addr readNextPC() { return nextPC; } 450 451 /** Returns the next NPC. This could be the speculative next NPC if it is 452 * called prior to the actual branch target being calculated. 453 */ 454 Addr readNextNPC() 455 { 456#if ISA_HAS_DELAY_SLOT 457 return nextNPC; 458#else 459 return nextPC + sizeof(TheISA::MachInst); 460#endif 461 } 462 463 Addr readNextMicroPC() 464 { 465 return nextMicroPC; 466 } 467 468 /** Set the predicted target of this current instruction. */ 469 void setPredTarg(Addr predicted_PC, Addr predicted_NPC, 470 Addr predicted_MicroPC) 471 { 472 predPC = predicted_PC; 473 predNPC = predicted_NPC; 474 predMicroPC = predicted_MicroPC; 475 } 476 477 /** Returns the predicted PC immediately after the branch. */ 478 Addr readPredPC() { return predPC; } 479 480 /** Returns the predicted PC two instructions after the branch */ 481 Addr readPredNPC() { return predNPC; } 482 483 /** Returns the predicted micro PC after the branch */ 484 Addr readPredMicroPC() { return predMicroPC; } 485 486 /** Returns whether the instruction was predicted taken or not. */ 487 bool readPredTaken() 488 { 489 return predTaken; 490 } 491 492 void setPredTaken(bool predicted_taken) 493 { 494 predTaken = predicted_taken; 495 } 496 497 /** Returns whether the instruction mispredicted. */ 498 bool mispredicted() 499 { 500 return readPredPC() != readNextPC() || 501 readPredNPC() != readNextNPC() || 502 readPredMicroPC() != readNextMicroPC(); 503 } 504 505 // 506 // Instruction types. Forward checks to StaticInst object. 507 // 508 bool isNop() const { return staticInst->isNop(); } 509 bool isMemRef() const { return staticInst->isMemRef(); } 510 bool isLoad() const { return staticInst->isLoad(); } 511 bool isStore() const { return staticInst->isStore(); } 512 bool isStoreConditional() const 513 { return staticInst->isStoreConditional(); } 514 bool isInstPrefetch() const { return staticInst->isInstPrefetch(); } 515 bool isDataPrefetch() const { return staticInst->isDataPrefetch(); } 516 bool isCopy() const { return staticInst->isCopy(); } 517 bool isInteger() const { return staticInst->isInteger(); } 518 bool isFloating() const { return staticInst->isFloating(); } 519 bool isControl() const { return staticInst->isControl(); } 520 bool isCall() const { return staticInst->isCall(); } 521 bool isReturn() const { return staticInst->isReturn(); } 522 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); } 523 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); } 524 bool isCondCtrl() const { return staticInst->isCondCtrl(); } 525 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); } 526 bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); } 527 bool isThreadSync() const { return staticInst->isThreadSync(); } 528 bool isSerializing() const { return staticInst->isSerializing(); } 529 bool isSerializeBefore() const 530 { return staticInst->isSerializeBefore() || status[SerializeBefore]; } 531 bool isSerializeAfter() const 532 { return staticInst->isSerializeAfter() || status[SerializeAfter]; } 533 bool isMemBarrier() const { return staticInst->isMemBarrier(); } 534 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); } 535 bool isNonSpeculative() const { return staticInst->isNonSpeculative(); } 536 bool isQuiesce() const { return staticInst->isQuiesce(); } 537 bool isIprAccess() const { return staticInst->isIprAccess(); } 538 bool isUnverifiable() const { return staticInst->isUnverifiable(); } 539 bool isSyscall() const { return staticInst->isSyscall(); } 540 bool isMacroop() const { return staticInst->isMacroop(); } 541 bool isMicroop() const { return staticInst->isMicroop(); } 542 bool isDelayedCommit() const { return staticInst->isDelayedCommit(); } 543 bool isLastMicroop() const { return staticInst->isLastMicroop(); } 544 bool isFirstMicroop() const { return staticInst->isFirstMicroop(); } 545 bool isMicroBranch() const { return staticInst->isMicroBranch(); } 546 547 /** Temporarily sets this instruction as a serialize before instruction. */ 548 void setSerializeBefore() { status.set(SerializeBefore); } 549 550 /** Clears the serializeBefore part of this instruction. */ 551 void clearSerializeBefore() { status.reset(SerializeBefore); } 552 553 /** Checks if this serializeBefore is only temporarily set. */ 554 bool isTempSerializeBefore() { return status[SerializeBefore]; } 555 556 /** Temporarily sets this instruction as a serialize after instruction. */ 557 void setSerializeAfter() { status.set(SerializeAfter); } 558 559 /** Clears the serializeAfter part of this instruction.*/ 560 void clearSerializeAfter() { status.reset(SerializeAfter); } 561 562 /** Checks if this serializeAfter is only temporarily set. */ 563 bool isTempSerializeAfter() { return status[SerializeAfter]; } 564 565 /** Sets the serialization part of this instruction as handled. */ 566 void setSerializeHandled() { status.set(SerializeHandled); } 567 568 /** Checks if the serialization part of this instruction has been 569 * handled. This does not apply to the temporary serializing 570 * state; it only applies to this instruction's own permanent 571 * serializing state. 572 */ 573 bool isSerializeHandled() { return status[SerializeHandled]; } 574 575 /** Returns the opclass of this instruction. */ 576 OpClass opClass() const { return staticInst->opClass(); } 577 578 /** Returns the branch target address. */ 579 Addr branchTarget() const { return staticInst->branchTarget(PC); } 580 581 /** Returns the number of source registers. */ 582 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); } 583 584 /** Returns the number of destination registers. */ 585 int8_t numDestRegs() const { return staticInst->numDestRegs(); } 586 587 // the following are used to track physical register usage 588 // for machines with separate int & FP reg files 589 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); } 590 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); } 591 592 /** Returns the logical register index of the i'th destination register. */ 593 RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); } 594 595 /** Returns the logical register index of the i'th source register. */ 596 RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); } 597 598 /** Returns the result of an integer instruction. */ 599 uint64_t readIntResult() { return instResult.integer; } 600 601 /** Returns the result of a floating point instruction. */ 602 float readFloatResult() { return (float)instResult.dbl; } 603 604 /** Returns the result of a floating point (double) instruction. */ 605 double readDoubleResult() { return instResult.dbl; } 606 607 /** Records an integer register being set to a value. */ 608 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) 609 { 610 if (recordResult) 611 instResult.integer = val; 612 } 613 614 /** Records an fp register being set to a value. */ 615 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val, 616 int width) 617 { 618 if (recordResult) { 619 if (width == 32) 620 instResult.dbl = (double)val; 621 else if (width == 64) 622 instResult.dbl = val; 623 else 624 panic("Unsupported width!"); 625 } 626 } 627 628 /** Records an fp register being set to a value. */ 629 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 630 { 631 if (recordResult) 632 instResult.dbl = (double)val; 633 } 634 635 /** Records an fp register being set to an integer value. */ 636 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val, 637 int width) 638 { 639 if (recordResult) 640 instResult.integer = val; 641 } 642 643 /** Records an fp register being set to an integer value. */ 644 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val) 645 { 646 if (recordResult) 647 instResult.integer = val; 648 } 649 650 /** Records that one of the source registers is ready. */ 651 void markSrcRegReady(); 652 653 /** Marks a specific register as ready. */ 654 void markSrcRegReady(RegIndex src_idx); 655 656 /** Returns if a source register is ready. */ 657 bool isReadySrcRegIdx(int idx) const 658 { 659 return this->_readySrcRegIdx[idx]; 660 } 661 662 /** Sets this instruction as completed. */ 663 void setCompleted() { status.set(Completed); } 664 665 /** Returns whether or not this instruction is completed. */ 666 bool isCompleted() const { return status[Completed]; } 667 668 /** Marks the result as ready. */ 669 void setResultReady() { status.set(ResultReady); } 670 671 /** Returns whether or not the result is ready. */ 672 bool isResultReady() const { return status[ResultReady]; } 673 674 /** Sets this instruction as ready to issue. */ 675 void setCanIssue() { status.set(CanIssue); } 676 677 /** Returns whether or not this instruction is ready to issue. */ 678 bool readyToIssue() const { return status[CanIssue]; } 679 680 /** Clears this instruction being able to issue. */ 681 void clearCanIssue() { status.reset(CanIssue); } 682 683 /** Sets this instruction as issued from the IQ. */ 684 void setIssued() { status.set(Issued); } 685 686 /** Returns whether or not this instruction has issued. */ 687 bool isIssued() const { return status[Issued]; } 688 689 /** Clears this instruction as being issued. */ 690 void clearIssued() { status.reset(Issued); } 691 692 /** Sets this instruction as executed. */ 693 void setExecuted() { status.set(Executed); } 694 695 /** Returns whether or not this instruction has executed. */ 696 bool isExecuted() const { return status[Executed]; } 697 698 /** Sets this instruction as ready to commit. */ 699 void setCanCommit() { status.set(CanCommit); } 700 701 /** Clears this instruction as being ready to commit. */ 702 void clearCanCommit() { status.reset(CanCommit); } 703 704 /** Returns whether or not this instruction is ready to commit. */ 705 bool readyToCommit() const { return status[CanCommit]; } 706 707 void setAtCommit() { status.set(AtCommit); } 708 709 bool isAtCommit() { return status[AtCommit]; } 710 711 /** Sets this instruction as committed. */ 712 void setCommitted() { status.set(Committed); } 713 714 /** Returns whether or not this instruction is committed. */ 715 bool isCommitted() const { return status[Committed]; } 716 717 /** Sets this instruction as squashed. */ 718 void setSquashed() { status.set(Squashed); } 719 720 /** Returns whether or not this instruction is squashed. */ 721 bool isSquashed() const { return status[Squashed]; } 722 723 //Instruction Queue Entry 724 //----------------------- 725 /** Sets this instruction as a entry the IQ. */ 726 void setInIQ() { status.set(IqEntry); } 727 728 /** Sets this instruction as a entry the IQ. */ 729 void clearInIQ() { status.reset(IqEntry); } 730 731 /** Returns whether or not this instruction has issued. */ 732 bool isInIQ() const { return status[IqEntry]; } 733 734 /** Sets this instruction as squashed in the IQ. */ 735 void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);} 736 737 /** Returns whether or not this instruction is squashed in the IQ. */ 738 bool isSquashedInIQ() const { return status[SquashedInIQ]; } 739 740 741 //Load / Store Queue Functions 742 //----------------------- 743 /** Sets this instruction as a entry the LSQ. */ 744 void setInLSQ() { status.set(LsqEntry); } 745 746 /** Sets this instruction as a entry the LSQ. */ 747 void removeInLSQ() { status.reset(LsqEntry); } 748 749 /** Returns whether or not this instruction is in the LSQ. */ 750 bool isInLSQ() const { return status[LsqEntry]; } 751 752 /** Sets this instruction as squashed in the LSQ. */ 753 void setSquashedInLSQ() { status.set(SquashedInLSQ);} 754 755 /** Returns whether or not this instruction is squashed in the LSQ. */ 756 bool isSquashedInLSQ() const { return status[SquashedInLSQ]; } 757 758 759 //Reorder Buffer Functions 760 //----------------------- 761 /** Sets this instruction as a entry the ROB. */ 762 void setInROB() { status.set(RobEntry); } 763 764 /** Sets this instruction as a entry the ROB. */ 765 void clearInROB() { status.reset(RobEntry); } 766 767 /** Returns whether or not this instruction is in the ROB. */ 768 bool isInROB() const { return status[RobEntry]; } 769 770 /** Sets this instruction as squashed in the ROB. */ 771 void setSquashedInROB() { status.set(SquashedInROB); } 772 773 /** Returns whether or not this instruction is squashed in the ROB. */ 774 bool isSquashedInROB() const { return status[SquashedInROB]; } 775 776 /** Read the PC of this instruction. */ 777 const Addr readPC() const { return PC; } 778 779 /**Read the micro PC of this instruction. */ 780 const Addr readMicroPC() const { return microPC; } 781 782 /** Set the next PC of this instruction (its actual target). */ 783 void setNextPC(Addr val) 784 { 785 nextPC = val; 786 } 787 788 /** Set the next NPC of this instruction (the target in Mips or Sparc).*/ 789 void setNextNPC(Addr val) 790 { 791#if ISA_HAS_DELAY_SLOT 792 nextNPC = val; 793#endif 794 } 795 796 void setNextMicroPC(Addr val) 797 { 798 nextMicroPC = val; 799 } 800 801 bool readPredicate() 802 { 803 return predicate; 804 } 805 806 void setPredicate(bool val) 807 { 808 predicate = val; 809 810 if (traceData) { 811 traceData->setPredicate(val); 812 } 813 } 814 815 /** Sets the ASID. */ 816 void setASID(short addr_space_id) { asid = addr_space_id; } 817 818 /** Sets the thread id. */ 819 void setTid(ThreadID tid) { threadNumber = tid; } 820 821 /** Sets the pointer to the thread state. */ 822 void setThreadState(ImplState *state) { thread = state; } 823 824 /** Returns the thread context. */ 825 ThreadContext *tcBase() { return thread->getTC(); } 826 827 private: 828 /** Instruction effective address. 829 * @todo: Consider if this is necessary or not. 830 */ 831 Addr instEffAddr; 832 833 /** Whether or not the effective address calculation is completed. 834 * @todo: Consider if this is necessary or not. 835 */ 836 bool eaCalcDone; 837 838 /** Is this instruction's memory access uncacheable. */ 839 bool isUncacheable; 840 841 /** Has this instruction generated a memory request. */ 842 bool reqMade; 843 844 public: 845 /** Sets the effective address. */ 846 void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; } 847 848 /** Returns the effective address. */ 849 const Addr &getEA() const { return instEffAddr; } 850 851 /** Returns whether or not the eff. addr. calculation has been completed. */ 852 bool doneEACalc() { return eaCalcDone; } 853 854 /** Returns whether or not the eff. addr. source registers are ready. */ 855 bool eaSrcsReady(); 856 857 /** Whether or not the memory operation is done. */ 858 bool memOpDone; 859 860 /** Is this instruction's memory access uncacheable. */ 861 bool uncacheable() { return isUncacheable; } 862 863 /** Has this instruction generated a memory request. */ 864 bool hasRequest() { return reqMade; } 865 866 public: 867 /** Load queue index. */ 868 int16_t lqIdx; 869 870 /** Store queue index. */ 871 int16_t sqIdx; 872 873 /** Iterator pointing to this BaseDynInst in the list of all insts. */ 874 ListIt instListIt; 875 876 /** Returns iterator to this instruction in the list of all insts. */ 877 ListIt &getInstListIt() { return instListIt; } 878 879 /** Sets iterator for this instruction in the list of all insts. */ 880 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; } 881 882 public: 883 /** Returns the number of consecutive store conditional failures. */ 884 unsigned readStCondFailures() 885 { return thread->storeCondFailures; } 886 887 /** Sets the number of consecutive store conditional failures. */ 888 void setStCondFailures(unsigned sc_failures) 889 { thread->storeCondFailures = sc_failures; } 890}; 891 892template<class Impl> 893Fault 894BaseDynInst<Impl>::readBytes(Addr addr, uint8_t *data, 895 unsigned size, unsigned flags) 896{ 897 reqMade = true; 898 Request *req = new Request(asid, addr, size, flags, this->PC, 899 thread->contextId(), threadNumber); 900 901 Request *sreqLow = NULL; 902 Request *sreqHigh = NULL; 903 904 // Only split the request if the ISA supports unaligned accesses. 905 if (TheISA::HasUnalignedMemAcc) { 906 splitRequest(req, sreqLow, sreqHigh); 907 } 908 initiateTranslation(req, sreqLow, sreqHigh, NULL, BaseTLB::Read); 909 910 if (fault == NoFault) { 911 effAddr = req->getVaddr(); 912 effAddrValid = true; 913 fault = cpu->read(req, sreqLow, sreqHigh, data, lqIdx); 914 } else { 915 // Commit will have to clean up whatever happened. Set this 916 // instruction as executed. 917 this->setExecuted(); 918 } 919 920 if (fault != NoFault) { 921 // Return a fixed value to keep simulation deterministic even 922 // along misspeculated paths. 923 bzero(data, size); 924 } 925 926 if (traceData) { 927 traceData->setAddr(addr); 928 } 929 930 return fault; 931} 932 933template<class Impl> 934template<class T> 935inline Fault 936BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags) 937{ 938 Fault fault = readBytes(addr, (uint8_t *)&data, sizeof(T), flags); 939 940 data = TheISA::gtoh(data); 941 942 if (traceData) { 943 traceData->setData(data); 944 } 945 946 return fault; 947} 948 949template<class Impl> 950Fault 951BaseDynInst<Impl>::writeBytes(uint8_t *data, unsigned size, 952 Addr addr, unsigned flags, uint64_t *res) 953{ 954 if (traceData) { 955 traceData->setAddr(addr); 956 } 957 958 reqMade = true; 959 Request *req = new Request(asid, addr, size, flags, this->PC, 960 thread->contextId(), threadNumber); 961 962 Request *sreqLow = NULL; 963 Request *sreqHigh = NULL; 964 965 // Only split the request if the ISA supports unaligned accesses. 966 if (TheISA::HasUnalignedMemAcc) { 967 splitRequest(req, sreqLow, sreqHigh); 968 } 969 initiateTranslation(req, sreqLow, sreqHigh, res, BaseTLB::Write); 970 971 if (fault == NoFault) { 972 effAddr = req->getVaddr(); 973 effAddrValid = true; 974 fault = cpu->write(req, sreqLow, sreqHigh, data, sqIdx); 975 } 976 977 return fault; 978} 979 980template<class Impl> 981template<class T> 982inline Fault 983BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res) 984{ 985 if (traceData) { 986 traceData->setData(data); 987 } 988 data = TheISA::htog(data); 989 return writeBytes((uint8_t *)&data, sizeof(T), addr, flags, res); 990} 991 992template<class Impl> 993inline void 994BaseDynInst<Impl>::splitRequest(RequestPtr req, RequestPtr &sreqLow, 995 RequestPtr &sreqHigh) 996{ 997 // Check to see if the request crosses the next level block boundary. 998 unsigned block_size = cpu->getDcachePort()->peerBlockSize(); 999 Addr addr = req->getVaddr(); 1000 Addr split_addr = roundDown(addr + req->getSize() - 1, block_size); 1001 assert(split_addr <= addr || split_addr - addr < block_size); 1002 1003 // Spans two blocks. 1004 if (split_addr > addr) { 1005 req->splitOnVaddr(split_addr, sreqLow, sreqHigh); 1006 } 1007} 1008 1009template<class Impl> 1010inline void 1011BaseDynInst<Impl>::initiateTranslation(RequestPtr req, RequestPtr sreqLow, 1012 RequestPtr sreqHigh, uint64_t *res, 1013 BaseTLB::Mode mode) 1014{ 1015 if (!TheISA::HasUnalignedMemAcc || sreqLow == NULL) { 1016 WholeTranslationState *state = 1017 new WholeTranslationState(req, NULL, res, mode); 1018 1019 // One translation if the request isn't split. 1020 DataTranslation<BaseDynInst<Impl> > *trans = 1021 new DataTranslation<BaseDynInst<Impl> >(this, state); 1022 cpu->dtb->translateTiming(req, thread->getTC(), trans, mode); 1023 } else { 1024 WholeTranslationState *state = 1025 new WholeTranslationState(req, sreqLow, sreqHigh, NULL, res, mode); 1026 1027 // Two translations when the request is split. 1028 DataTranslation<BaseDynInst<Impl> > *stransLow = 1029 new DataTranslation<BaseDynInst<Impl> >(this, state, 0); 1030 DataTranslation<BaseDynInst<Impl> > *stransHigh = 1031 new DataTranslation<BaseDynInst<Impl> >(this, state, 1); 1032 1033 cpu->dtb->translateTiming(sreqLow, thread->getTC(), stransLow, mode); 1034 cpu->dtb->translateTiming(sreqHigh, thread->getTC(), stransHigh, mode); 1035 } 1036} 1037 1038template<class Impl> 1039inline void 1040BaseDynInst<Impl>::finishTranslation(WholeTranslationState *state) 1041{ 1042 fault = state->getFault(); 1043 1044 if (state->isUncacheable()) 1045 isUncacheable = true; 1046 1047 if (fault == NoFault) { 1048 physEffAddr = state->getPaddr(); 1049 memReqFlags = state->getFlags(); 1050 1051 if (state->mainReq->isCondSwap()) { 1052 assert(state->res); 1053 state->mainReq->setExtraData(*state->res); 1054 } 1055 1056 } else { 1057 state->deleteReqs(); 1058 } 1059 delete state; 1060} 1061 1062#endif // __CPU_BASE_DYN_INST_HH__ 1063