base_dyn_inst.hh revision 7577
11060SN/A/* 22702Sktlim@umich.edu * Copyright (c) 2004-2006 The Regents of The University of Michigan 36973Stjones1@inf.ed.ac.uk * Copyright (c) 2009 The University of Edinburgh 41060SN/A * All rights reserved. 51060SN/A * 61060SN/A * Redistribution and use in source and binary forms, with or without 71060SN/A * modification, are permitted provided that the following conditions are 81060SN/A * met: redistributions of source code must retain the above copyright 91060SN/A * notice, this list of conditions and the following disclaimer; 101060SN/A * redistributions in binary form must reproduce the above copyright 111060SN/A * notice, this list of conditions and the following disclaimer in the 121060SN/A * documentation and/or other materials provided with the distribution; 131060SN/A * neither the name of the copyright holders nor the names of its 141060SN/A * contributors may be used to endorse or promote products derived from 151060SN/A * this software without specific prior written permission. 161060SN/A * 171060SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 181060SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 191060SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 201060SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 211060SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 221060SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 231060SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 241060SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 251060SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 261060SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 271060SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282665Ssaidi@eecs.umich.edu * 292665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 306973Stjones1@inf.ed.ac.uk * Timothy M. Jones 311060SN/A */ 321060SN/A 331464SN/A#ifndef __CPU_BASE_DYN_INST_HH__ 341464SN/A#define __CPU_BASE_DYN_INST_HH__ 351060SN/A 362731Sktlim@umich.edu#include <bitset> 372292SN/A#include <list> 381464SN/A#include <string> 391060SN/A 402669Sktlim@umich.edu#include "arch/faults.hh" 411060SN/A#include "base/fast_alloc.hh" 421060SN/A#include "base/trace.hh" 431858SN/A#include "config/full_system.hh" 446658Snate@binkert.org#include "config/the_isa.hh" 453770Sgblack@eecs.umich.edu#include "cpu/o3/comm.hh" 461464SN/A#include "cpu/exetrace.hh" 471464SN/A#include "cpu/inst_seq.hh" 482669Sktlim@umich.edu#include "cpu/op_class.hh" 491060SN/A#include "cpu/static_inst.hh" 506973Stjones1@inf.ed.ac.uk#include "cpu/translation.hh" 512669Sktlim@umich.edu#include "mem/packet.hh" 522292SN/A#include "sim/system.hh" 536023Snate@binkert.org#include "sim/tlb.hh" 541060SN/A 551060SN/A/** 561060SN/A * @file 571060SN/A * Defines a dynamic instruction context. 581060SN/A */ 591060SN/A 601061SN/A// Forward declaration. 611061SN/Aclass StaticInstPtr; 621060SN/A 631060SN/Atemplate <class Impl> 641061SN/Aclass BaseDynInst : public FastAlloc, public RefCounted 651060SN/A{ 661060SN/A public: 671060SN/A // Typedef for the CPU. 682733Sktlim@umich.edu typedef typename Impl::CPUType ImplCPU; 692733Sktlim@umich.edu typedef typename ImplCPU::ImplState ImplState; 701060SN/A 712292SN/A // Logical register index type. 722107SN/A typedef TheISA::RegIndex RegIndex; 732690Sktlim@umich.edu // Integer register type. 742107SN/A typedef TheISA::IntReg IntReg; 752690Sktlim@umich.edu // Floating point register type. 762690Sktlim@umich.edu typedef TheISA::FloatReg FloatReg; 771060SN/A 782292SN/A // The DynInstPtr type. 792292SN/A typedef typename Impl::DynInstPtr DynInstPtr; 802292SN/A 812292SN/A // The list of instructions iterator type. 822292SN/A typedef typename std::list<DynInstPtr>::iterator ListIt; 832292SN/A 841060SN/A enum { 855543Ssaidi@eecs.umich.edu MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs 865543Ssaidi@eecs.umich.edu MaxInstDestRegs = TheISA::MaxInstDestRegs, /// Max dest regs 871060SN/A }; 881060SN/A 892292SN/A /** The StaticInst used by this BaseDynInst. */ 902107SN/A StaticInstPtr staticInst; 911060SN/A 921060SN/A //////////////////////////////////////////// 931060SN/A // 941060SN/A // INSTRUCTION EXECUTION 951060SN/A // 961060SN/A //////////////////////////////////////////// 972292SN/A /** InstRecord that tracks this instructions. */ 981060SN/A Trace::InstRecord *traceData; 991060SN/A 1005358Sgblack@eecs.umich.edu void demapPage(Addr vaddr, uint64_t asn) 1015358Sgblack@eecs.umich.edu { 1025358Sgblack@eecs.umich.edu cpu->demapPage(vaddr, asn); 1035358Sgblack@eecs.umich.edu } 1045358Sgblack@eecs.umich.edu void demapInstPage(Addr vaddr, uint64_t asn) 1055358Sgblack@eecs.umich.edu { 1065358Sgblack@eecs.umich.edu cpu->demapPage(vaddr, asn); 1075358Sgblack@eecs.umich.edu } 1085358Sgblack@eecs.umich.edu void demapDataPage(Addr vaddr, uint64_t asn) 1095358Sgblack@eecs.umich.edu { 1105358Sgblack@eecs.umich.edu cpu->demapPage(vaddr, asn); 1115358Sgblack@eecs.umich.edu } 1125358Sgblack@eecs.umich.edu 1132292SN/A /** 1142292SN/A * Does a read to a given address. 1152292SN/A * @param addr The address to read. 1162292SN/A * @param data The read's data is written into this parameter. 1172292SN/A * @param flags The request's flags. 1182292SN/A * @return Returns any fault due to the read. 1192292SN/A */ 1201060SN/A template <class T> 1212132SN/A Fault read(Addr addr, T &data, unsigned flags); 1221060SN/A 1237520Sgblack@eecs.umich.edu Fault readBytes(Addr addr, uint8_t *data, unsigned size, unsigned flags); 1247520Sgblack@eecs.umich.edu 1252292SN/A /** 1262292SN/A * Does a write to a given address. 1272292SN/A * @param data The data to be written. 1282292SN/A * @param addr The address to write to. 1292292SN/A * @param flags The request's flags. 1302292SN/A * @param res The result of the write (for load locked/store conditionals). 1312292SN/A * @return Returns any fault due to the write. 1322292SN/A */ 1331060SN/A template <class T> 1346973Stjones1@inf.ed.ac.uk Fault write(T data, Addr addr, unsigned flags, uint64_t *res); 1356973Stjones1@inf.ed.ac.uk 1367520Sgblack@eecs.umich.edu Fault writeBytes(uint8_t *data, unsigned size, 1377520Sgblack@eecs.umich.edu Addr addr, unsigned flags, uint64_t *res); 1387520Sgblack@eecs.umich.edu 1396974Stjones1@inf.ed.ac.uk /** Splits a request in two if it crosses a dcache block. */ 1406974Stjones1@inf.ed.ac.uk void splitRequest(RequestPtr req, RequestPtr &sreqLow, 1416974Stjones1@inf.ed.ac.uk RequestPtr &sreqHigh); 1426974Stjones1@inf.ed.ac.uk 1436973Stjones1@inf.ed.ac.uk /** Initiate a DTB address translation. */ 1446974Stjones1@inf.ed.ac.uk void initiateTranslation(RequestPtr req, RequestPtr sreqLow, 1456974Stjones1@inf.ed.ac.uk RequestPtr sreqHigh, uint64_t *res, 1466973Stjones1@inf.ed.ac.uk BaseTLB::Mode mode); 1476973Stjones1@inf.ed.ac.uk 1486973Stjones1@inf.ed.ac.uk /** Finish a DTB address translation. */ 1496973Stjones1@inf.ed.ac.uk void finishTranslation(WholeTranslationState *state); 1501060SN/A 1511060SN/A void prefetch(Addr addr, unsigned flags); 1521060SN/A void writeHint(Addr addr, int size, unsigned flags); 1532132SN/A Fault copySrcTranslate(Addr src); 1542132SN/A Fault copy(Addr dest); 1551060SN/A 1561684SN/A /** @todo: Consider making this private. */ 1571060SN/A public: 1581060SN/A /** The sequence number of the instruction. */ 1591060SN/A InstSeqNum seqNum; 1601060SN/A 1612731Sktlim@umich.edu enum Status { 1622731Sktlim@umich.edu IqEntry, /// Instruction is in the IQ 1632731Sktlim@umich.edu RobEntry, /// Instruction is in the ROB 1642731Sktlim@umich.edu LsqEntry, /// Instruction is in the LSQ 1652731Sktlim@umich.edu Completed, /// Instruction has completed 1662731Sktlim@umich.edu ResultReady, /// Instruction has its result 1672731Sktlim@umich.edu CanIssue, /// Instruction can issue and execute 1682731Sktlim@umich.edu Issued, /// Instruction has issued 1692731Sktlim@umich.edu Executed, /// Instruction has executed 1702731Sktlim@umich.edu CanCommit, /// Instruction can commit 1712731Sktlim@umich.edu AtCommit, /// Instruction has reached commit 1722731Sktlim@umich.edu Committed, /// Instruction has committed 1732731Sktlim@umich.edu Squashed, /// Instruction is squashed 1742731Sktlim@umich.edu SquashedInIQ, /// Instruction is squashed in the IQ 1752731Sktlim@umich.edu SquashedInLSQ, /// Instruction is squashed in the LSQ 1762731Sktlim@umich.edu SquashedInROB, /// Instruction is squashed in the ROB 1772731Sktlim@umich.edu RecoverInst, /// Is a recover instruction 1782731Sktlim@umich.edu BlockingInst, /// Is a blocking instruction 1792731Sktlim@umich.edu ThreadsyncWait, /// Is a thread synchronization instruction 1802731Sktlim@umich.edu SerializeBefore, /// Needs to serialize on 1812731Sktlim@umich.edu /// instructions ahead of it 1822731Sktlim@umich.edu SerializeAfter, /// Needs to serialize instructions behind it 1832731Sktlim@umich.edu SerializeHandled, /// Serialization has been handled 1842731Sktlim@umich.edu NumStatus 1852731Sktlim@umich.edu }; 1862292SN/A 1872731Sktlim@umich.edu /** The status of this BaseDynInst. Several bits can be set. */ 1882731Sktlim@umich.edu std::bitset<NumStatus> status; 1891060SN/A 1901060SN/A /** The thread this instruction is from. */ 1916221Snate@binkert.org ThreadID threadNumber; 1921060SN/A 1931060SN/A /** data address space ID, for loads & stores. */ 1941060SN/A short asid; 1951060SN/A 1962292SN/A /** How many source registers are ready. */ 1972292SN/A unsigned readyRegs; 1982292SN/A 1992733Sktlim@umich.edu /** Pointer to the Impl's CPU object. */ 2002733Sktlim@umich.edu ImplCPU *cpu; 2011060SN/A 2022680Sktlim@umich.edu /** Pointer to the thread state. */ 2032292SN/A ImplState *thread; 2041060SN/A 2051060SN/A /** The kind of fault this instruction has generated. */ 2062132SN/A Fault fault; 2071060SN/A 2082702Sktlim@umich.edu /** Pointer to the data for the memory access. */ 2092669Sktlim@umich.edu uint8_t *memData; 2102292SN/A 2111060SN/A /** The effective virtual address (lds & stores only). */ 2121060SN/A Addr effAddr; 2131060SN/A 2144032Sktlim@umich.edu /** Is the effective virtual address valid. */ 2154032Sktlim@umich.edu bool effAddrValid; 2164032Sktlim@umich.edu 2171060SN/A /** The effective physical address. */ 2181060SN/A Addr physEffAddr; 2191060SN/A 2201060SN/A /** Effective virtual address for a copy source. */ 2211060SN/A Addr copySrcEffAddr; 2221060SN/A 2231060SN/A /** Effective physical address for a copy source. */ 2241060SN/A Addr copySrcPhysEffAddr; 2251060SN/A 2261060SN/A /** The memory request flags (from translation). */ 2271060SN/A unsigned memReqFlags; 2281060SN/A 2291464SN/A union Result { 2301464SN/A uint64_t integer; 2312356SN/A// float fp; 2321464SN/A double dbl; 2331464SN/A }; 2341060SN/A 2351464SN/A /** The result of the instruction; assumes for now that there's only one 2361464SN/A * destination register. 2371464SN/A */ 2381464SN/A Result instResult; 2391060SN/A 2403326Sktlim@umich.edu /** Records changes to result? */ 2413326Sktlim@umich.edu bool recordResult; 2423326Sktlim@umich.edu 2431060SN/A /** PC of this instruction. */ 2441060SN/A Addr PC; 2451060SN/A 2464636Sgblack@eecs.umich.edu /** Micro PC of this instruction. */ 2474636Sgblack@eecs.umich.edu Addr microPC; 2484636Sgblack@eecs.umich.edu 2493965Sgblack@eecs.umich.edu protected: 2501060SN/A /** Next non-speculative PC. It is not filled in at fetch, but rather 2511060SN/A * once the target of the branch is truly known (either decode or 2521060SN/A * execute). 2531060SN/A */ 2541060SN/A Addr nextPC; 2551060SN/A 2562935Sksewell@umich.edu /** Next non-speculative NPC. Target PC for Mips or Sparc. */ 2572935Sksewell@umich.edu Addr nextNPC; 2582935Sksewell@umich.edu 2594636Sgblack@eecs.umich.edu /** Next non-speculative micro PC. */ 2604636Sgblack@eecs.umich.edu Addr nextMicroPC; 2614636Sgblack@eecs.umich.edu 2621060SN/A /** Predicted next PC. */ 2631060SN/A Addr predPC; 2641060SN/A 2653794Sgblack@eecs.umich.edu /** Predicted next NPC. */ 2663794Sgblack@eecs.umich.edu Addr predNPC; 2673794Sgblack@eecs.umich.edu 2684636Sgblack@eecs.umich.edu /** Predicted next microPC */ 2694636Sgblack@eecs.umich.edu Addr predMicroPC; 2704636Sgblack@eecs.umich.edu 2713794Sgblack@eecs.umich.edu /** If this is a branch that was predicted taken */ 2723794Sgblack@eecs.umich.edu bool predTaken; 2733794Sgblack@eecs.umich.edu 2743965Sgblack@eecs.umich.edu public: 2753965Sgblack@eecs.umich.edu 2762292SN/A#ifdef DEBUG 2772292SN/A void dumpSNList(); 2782292SN/A#endif 2792292SN/A 2802292SN/A /** Whether or not the source register is ready. 2812292SN/A * @todo: Not sure this should be here vs the derived class. 2821060SN/A */ 2831060SN/A bool _readySrcRegIdx[MaxInstSrcRegs]; 2841060SN/A 2853770Sgblack@eecs.umich.edu protected: 2863770Sgblack@eecs.umich.edu /** Flattened register index of the destination registers of this 2873770Sgblack@eecs.umich.edu * instruction. 2883770Sgblack@eecs.umich.edu */ 2893770Sgblack@eecs.umich.edu TheISA::RegIndex _flatDestRegIdx[TheISA::MaxInstDestRegs]; 2903770Sgblack@eecs.umich.edu 2913770Sgblack@eecs.umich.edu /** Flattened register index of the source registers of this 2923770Sgblack@eecs.umich.edu * instruction. 2933770Sgblack@eecs.umich.edu */ 2943770Sgblack@eecs.umich.edu TheISA::RegIndex _flatSrcRegIdx[TheISA::MaxInstSrcRegs]; 2953770Sgblack@eecs.umich.edu 2963770Sgblack@eecs.umich.edu /** Physical register index of the destination registers of this 2973770Sgblack@eecs.umich.edu * instruction. 2983770Sgblack@eecs.umich.edu */ 2993770Sgblack@eecs.umich.edu PhysRegIndex _destRegIdx[TheISA::MaxInstDestRegs]; 3003770Sgblack@eecs.umich.edu 3013770Sgblack@eecs.umich.edu /** Physical register index of the source registers of this 3023770Sgblack@eecs.umich.edu * instruction. 3033770Sgblack@eecs.umich.edu */ 3043770Sgblack@eecs.umich.edu PhysRegIndex _srcRegIdx[TheISA::MaxInstSrcRegs]; 3053770Sgblack@eecs.umich.edu 3063770Sgblack@eecs.umich.edu /** Physical register index of the previous producers of the 3073770Sgblack@eecs.umich.edu * architected destinations. 3083770Sgblack@eecs.umich.edu */ 3093770Sgblack@eecs.umich.edu PhysRegIndex _prevDestRegIdx[TheISA::MaxInstDestRegs]; 3103770Sgblack@eecs.umich.edu 3111060SN/A public: 3123770Sgblack@eecs.umich.edu 3133770Sgblack@eecs.umich.edu /** Returns the physical register index of the i'th destination 3143770Sgblack@eecs.umich.edu * register. 3153770Sgblack@eecs.umich.edu */ 3163770Sgblack@eecs.umich.edu PhysRegIndex renamedDestRegIdx(int idx) const 3173770Sgblack@eecs.umich.edu { 3183770Sgblack@eecs.umich.edu return _destRegIdx[idx]; 3193770Sgblack@eecs.umich.edu } 3203770Sgblack@eecs.umich.edu 3213770Sgblack@eecs.umich.edu /** Returns the physical register index of the i'th source register. */ 3223770Sgblack@eecs.umich.edu PhysRegIndex renamedSrcRegIdx(int idx) const 3233770Sgblack@eecs.umich.edu { 3243770Sgblack@eecs.umich.edu return _srcRegIdx[idx]; 3253770Sgblack@eecs.umich.edu } 3263770Sgblack@eecs.umich.edu 3273770Sgblack@eecs.umich.edu /** Returns the flattened register index of the i'th destination 3283770Sgblack@eecs.umich.edu * register. 3293770Sgblack@eecs.umich.edu */ 3303770Sgblack@eecs.umich.edu TheISA::RegIndex flattenedDestRegIdx(int idx) const 3313770Sgblack@eecs.umich.edu { 3323770Sgblack@eecs.umich.edu return _flatDestRegIdx[idx]; 3333770Sgblack@eecs.umich.edu } 3343770Sgblack@eecs.umich.edu 3353770Sgblack@eecs.umich.edu /** Returns the flattened register index of the i'th source register */ 3363770Sgblack@eecs.umich.edu TheISA::RegIndex flattenedSrcRegIdx(int idx) const 3373770Sgblack@eecs.umich.edu { 3383770Sgblack@eecs.umich.edu return _flatSrcRegIdx[idx]; 3393770Sgblack@eecs.umich.edu } 3403770Sgblack@eecs.umich.edu 3413770Sgblack@eecs.umich.edu /** Returns the physical register index of the previous physical register 3423770Sgblack@eecs.umich.edu * that remapped to the same logical register index. 3433770Sgblack@eecs.umich.edu */ 3443770Sgblack@eecs.umich.edu PhysRegIndex prevDestRegIdx(int idx) const 3453770Sgblack@eecs.umich.edu { 3463770Sgblack@eecs.umich.edu return _prevDestRegIdx[idx]; 3473770Sgblack@eecs.umich.edu } 3483770Sgblack@eecs.umich.edu 3493770Sgblack@eecs.umich.edu /** Renames a destination register to a physical register. Also records 3503770Sgblack@eecs.umich.edu * the previous physical register that the logical register mapped to. 3513770Sgblack@eecs.umich.edu */ 3523770Sgblack@eecs.umich.edu void renameDestReg(int idx, 3533770Sgblack@eecs.umich.edu PhysRegIndex renamed_dest, 3543770Sgblack@eecs.umich.edu PhysRegIndex previous_rename) 3553770Sgblack@eecs.umich.edu { 3563770Sgblack@eecs.umich.edu _destRegIdx[idx] = renamed_dest; 3573770Sgblack@eecs.umich.edu _prevDestRegIdx[idx] = previous_rename; 3583770Sgblack@eecs.umich.edu } 3593770Sgblack@eecs.umich.edu 3603770Sgblack@eecs.umich.edu /** Renames a source logical register to the physical register which 3613770Sgblack@eecs.umich.edu * has/will produce that logical register's result. 3623770Sgblack@eecs.umich.edu * @todo: add in whether or not the source register is ready. 3633770Sgblack@eecs.umich.edu */ 3643770Sgblack@eecs.umich.edu void renameSrcReg(int idx, PhysRegIndex renamed_src) 3653770Sgblack@eecs.umich.edu { 3663770Sgblack@eecs.umich.edu _srcRegIdx[idx] = renamed_src; 3673770Sgblack@eecs.umich.edu } 3683770Sgblack@eecs.umich.edu 3693770Sgblack@eecs.umich.edu /** Flattens a source architectural register index into a logical index. 3703770Sgblack@eecs.umich.edu */ 3713770Sgblack@eecs.umich.edu void flattenSrcReg(int idx, TheISA::RegIndex flattened_src) 3723770Sgblack@eecs.umich.edu { 3733770Sgblack@eecs.umich.edu _flatSrcRegIdx[idx] = flattened_src; 3743770Sgblack@eecs.umich.edu } 3753770Sgblack@eecs.umich.edu 3763770Sgblack@eecs.umich.edu /** Flattens a destination architectural register index into a logical 3773770Sgblack@eecs.umich.edu * index. 3783770Sgblack@eecs.umich.edu */ 3793770Sgblack@eecs.umich.edu void flattenDestReg(int idx, TheISA::RegIndex flattened_dest) 3803770Sgblack@eecs.umich.edu { 3813770Sgblack@eecs.umich.edu _flatDestRegIdx[idx] = flattened_dest; 3823770Sgblack@eecs.umich.edu } 3834636Sgblack@eecs.umich.edu /** BaseDynInst constructor given a binary instruction. 3844636Sgblack@eecs.umich.edu * @param staticInst A StaticInstPtr to the underlying instruction. 3854636Sgblack@eecs.umich.edu * @param PC The PC of the instruction. 3864636Sgblack@eecs.umich.edu * @param pred_PC The predicted next PC. 3874636Sgblack@eecs.umich.edu * @param pred_NPC The predicted next NPC. 3884636Sgblack@eecs.umich.edu * @param seq_num The sequence number of the instruction. 3894636Sgblack@eecs.umich.edu * @param cpu Pointer to the instruction's CPU. 3904636Sgblack@eecs.umich.edu */ 3914636Sgblack@eecs.umich.edu BaseDynInst(StaticInstPtr staticInst, Addr PC, Addr NPC, Addr microPC, 3924636Sgblack@eecs.umich.edu Addr pred_PC, Addr pred_NPC, Addr pred_MicroPC, 3934636Sgblack@eecs.umich.edu InstSeqNum seq_num, ImplCPU *cpu); 3943770Sgblack@eecs.umich.edu 3952292SN/A /** BaseDynInst constructor given a binary instruction. 3962292SN/A * @param inst The binary instruction. 3972292SN/A * @param PC The PC of the instruction. 3982292SN/A * @param pred_PC The predicted next PC. 3993794Sgblack@eecs.umich.edu * @param pred_NPC The predicted next NPC. 4002292SN/A * @param seq_num The sequence number of the instruction. 4012292SN/A * @param cpu Pointer to the instruction's CPU. 4022292SN/A */ 4034636Sgblack@eecs.umich.edu BaseDynInst(TheISA::ExtMachInst inst, Addr PC, Addr NPC, Addr microPC, 4044636Sgblack@eecs.umich.edu Addr pred_PC, Addr pred_NPC, Addr pred_MicroPC, 4053770Sgblack@eecs.umich.edu InstSeqNum seq_num, ImplCPU *cpu); 4061060SN/A 4072292SN/A /** BaseDynInst constructor given a StaticInst pointer. 4082292SN/A * @param _staticInst The StaticInst for this BaseDynInst. 4092292SN/A */ 4102107SN/A BaseDynInst(StaticInstPtr &_staticInst); 4111060SN/A 4121060SN/A /** BaseDynInst destructor. */ 4131060SN/A ~BaseDynInst(); 4141060SN/A 4151464SN/A private: 4161684SN/A /** Function to initialize variables in the constructors. */ 4171464SN/A void initVars(); 4181060SN/A 4191464SN/A public: 4201060SN/A /** Dumps out contents of this BaseDynInst. */ 4211060SN/A void dump(); 4221060SN/A 4231060SN/A /** Dumps out contents of this BaseDynInst into given string. */ 4241060SN/A void dump(std::string &outstring); 4251060SN/A 4263326Sktlim@umich.edu /** Read this CPU's ID. */ 4275712Shsul@eecs.umich.edu int cpuId() { return cpu->cpuId(); } 4283326Sktlim@umich.edu 4295714Shsul@eecs.umich.edu /** Read this context's system-wide ID **/ 4305714Shsul@eecs.umich.edu int contextId() { return thread->contextId(); } 4315714Shsul@eecs.umich.edu 4321060SN/A /** Returns the fault type. */ 4332132SN/A Fault getFault() { return fault; } 4341060SN/A 4351060SN/A /** Checks whether or not this instruction has had its branch target 4361060SN/A * calculated yet. For now it is not utilized and is hacked to be 4371060SN/A * always false. 4382292SN/A * @todo: Actually use this instruction. 4391060SN/A */ 4401060SN/A bool doneTargCalc() { return false; } 4411060SN/A 4421684SN/A /** Returns the next PC. This could be the speculative next PC if it is 4431684SN/A * called prior to the actual branch target being calculated. 4441684SN/A */ 4451060SN/A Addr readNextPC() { return nextPC; } 4461060SN/A 4472935Sksewell@umich.edu /** Returns the next NPC. This could be the speculative next NPC if it is 4482935Sksewell@umich.edu * called prior to the actual branch target being calculated. 4492935Sksewell@umich.edu */ 4503965Sgblack@eecs.umich.edu Addr readNextNPC() 4513965Sgblack@eecs.umich.edu { 4523965Sgblack@eecs.umich.edu#if ISA_HAS_DELAY_SLOT 4533965Sgblack@eecs.umich.edu return nextNPC; 4543965Sgblack@eecs.umich.edu#else 4553965Sgblack@eecs.umich.edu return nextPC + sizeof(TheISA::MachInst); 4563965Sgblack@eecs.umich.edu#endif 4573965Sgblack@eecs.umich.edu } 4582935Sksewell@umich.edu 4594636Sgblack@eecs.umich.edu Addr readNextMicroPC() 4604636Sgblack@eecs.umich.edu { 4614636Sgblack@eecs.umich.edu return nextMicroPC; 4624636Sgblack@eecs.umich.edu } 4634636Sgblack@eecs.umich.edu 4641060SN/A /** Set the predicted target of this current instruction. */ 4654636Sgblack@eecs.umich.edu void setPredTarg(Addr predicted_PC, Addr predicted_NPC, 4664636Sgblack@eecs.umich.edu Addr predicted_MicroPC) 4673794Sgblack@eecs.umich.edu { 4683794Sgblack@eecs.umich.edu predPC = predicted_PC; 4693794Sgblack@eecs.umich.edu predNPC = predicted_NPC; 4704636Sgblack@eecs.umich.edu predMicroPC = predicted_MicroPC; 4713794Sgblack@eecs.umich.edu } 4721060SN/A 4733794Sgblack@eecs.umich.edu /** Returns the predicted PC immediately after the branch. */ 4743794Sgblack@eecs.umich.edu Addr readPredPC() { return predPC; } 4753794Sgblack@eecs.umich.edu 4763794Sgblack@eecs.umich.edu /** Returns the predicted PC two instructions after the branch */ 4773794Sgblack@eecs.umich.edu Addr readPredNPC() { return predNPC; } 4781060SN/A 4794636Sgblack@eecs.umich.edu /** Returns the predicted micro PC after the branch */ 4804636Sgblack@eecs.umich.edu Addr readPredMicroPC() { return predMicroPC; } 4814636Sgblack@eecs.umich.edu 4821060SN/A /** Returns whether the instruction was predicted taken or not. */ 4833794Sgblack@eecs.umich.edu bool readPredTaken() 4843794Sgblack@eecs.umich.edu { 4853794Sgblack@eecs.umich.edu return predTaken; 4863794Sgblack@eecs.umich.edu } 4873794Sgblack@eecs.umich.edu 4883794Sgblack@eecs.umich.edu void setPredTaken(bool predicted_taken) 4893794Sgblack@eecs.umich.edu { 4903794Sgblack@eecs.umich.edu predTaken = predicted_taken; 4913794Sgblack@eecs.umich.edu } 4921060SN/A 4931060SN/A /** Returns whether the instruction mispredicted. */ 4942935Sksewell@umich.edu bool mispredicted() 4953794Sgblack@eecs.umich.edu { 4963965Sgblack@eecs.umich.edu return readPredPC() != readNextPC() || 4974636Sgblack@eecs.umich.edu readPredNPC() != readNextNPC() || 4984636Sgblack@eecs.umich.edu readPredMicroPC() != readNextMicroPC(); 4993794Sgblack@eecs.umich.edu } 5003794Sgblack@eecs.umich.edu 5011060SN/A // 5021060SN/A // Instruction types. Forward checks to StaticInst object. 5031060SN/A // 5045543Ssaidi@eecs.umich.edu bool isNop() const { return staticInst->isNop(); } 5055543Ssaidi@eecs.umich.edu bool isMemRef() const { return staticInst->isMemRef(); } 5065543Ssaidi@eecs.umich.edu bool isLoad() const { return staticInst->isLoad(); } 5075543Ssaidi@eecs.umich.edu bool isStore() const { return staticInst->isStore(); } 5082336SN/A bool isStoreConditional() const 5092336SN/A { return staticInst->isStoreConditional(); } 5101060SN/A bool isInstPrefetch() const { return staticInst->isInstPrefetch(); } 5111060SN/A bool isDataPrefetch() const { return staticInst->isDataPrefetch(); } 5121060SN/A bool isCopy() const { return staticInst->isCopy(); } 5135543Ssaidi@eecs.umich.edu bool isInteger() const { return staticInst->isInteger(); } 5145543Ssaidi@eecs.umich.edu bool isFloating() const { return staticInst->isFloating(); } 5155543Ssaidi@eecs.umich.edu bool isControl() const { return staticInst->isControl(); } 5165543Ssaidi@eecs.umich.edu bool isCall() const { return staticInst->isCall(); } 5175543Ssaidi@eecs.umich.edu bool isReturn() const { return staticInst->isReturn(); } 5185543Ssaidi@eecs.umich.edu bool isDirectCtrl() const { return staticInst->isDirectCtrl(); } 5191060SN/A bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); } 5205543Ssaidi@eecs.umich.edu bool isCondCtrl() const { return staticInst->isCondCtrl(); } 5215543Ssaidi@eecs.umich.edu bool isUncondCtrl() const { return staticInst->isUncondCtrl(); } 5222935Sksewell@umich.edu bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); } 5231060SN/A bool isThreadSync() const { return staticInst->isThreadSync(); } 5241060SN/A bool isSerializing() const { return staticInst->isSerializing(); } 5252292SN/A bool isSerializeBefore() const 5262731Sktlim@umich.edu { return staticInst->isSerializeBefore() || status[SerializeBefore]; } 5272292SN/A bool isSerializeAfter() const 5282731Sktlim@umich.edu { return staticInst->isSerializeAfter() || status[SerializeAfter]; } 5291060SN/A bool isMemBarrier() const { return staticInst->isMemBarrier(); } 5301060SN/A bool isWriteBarrier() const { return staticInst->isWriteBarrier(); } 5311060SN/A bool isNonSpeculative() const { return staticInst->isNonSpeculative(); } 5322292SN/A bool isQuiesce() const { return staticInst->isQuiesce(); } 5332336SN/A bool isIprAccess() const { return staticInst->isIprAccess(); } 5342308SN/A bool isUnverifiable() const { return staticInst->isUnverifiable(); } 5354828Sgblack@eecs.umich.edu bool isSyscall() const { return staticInst->isSyscall(); } 5364654Sgblack@eecs.umich.edu bool isMacroop() const { return staticInst->isMacroop(); } 5374654Sgblack@eecs.umich.edu bool isMicroop() const { return staticInst->isMicroop(); } 5384636Sgblack@eecs.umich.edu bool isDelayedCommit() const { return staticInst->isDelayedCommit(); } 5394654Sgblack@eecs.umich.edu bool isLastMicroop() const { return staticInst->isLastMicroop(); } 5404654Sgblack@eecs.umich.edu bool isFirstMicroop() const { return staticInst->isFirstMicroop(); } 5414636Sgblack@eecs.umich.edu bool isMicroBranch() const { return staticInst->isMicroBranch(); } 5422292SN/A 5432292SN/A /** Temporarily sets this instruction as a serialize before instruction. */ 5442731Sktlim@umich.edu void setSerializeBefore() { status.set(SerializeBefore); } 5452292SN/A 5462292SN/A /** Clears the serializeBefore part of this instruction. */ 5472731Sktlim@umich.edu void clearSerializeBefore() { status.reset(SerializeBefore); } 5482292SN/A 5492292SN/A /** Checks if this serializeBefore is only temporarily set. */ 5502731Sktlim@umich.edu bool isTempSerializeBefore() { return status[SerializeBefore]; } 5512292SN/A 5522292SN/A /** Temporarily sets this instruction as a serialize after instruction. */ 5532731Sktlim@umich.edu void setSerializeAfter() { status.set(SerializeAfter); } 5542292SN/A 5552292SN/A /** Clears the serializeAfter part of this instruction.*/ 5562731Sktlim@umich.edu void clearSerializeAfter() { status.reset(SerializeAfter); } 5572292SN/A 5582292SN/A /** Checks if this serializeAfter is only temporarily set. */ 5592731Sktlim@umich.edu bool isTempSerializeAfter() { return status[SerializeAfter]; } 5602292SN/A 5612731Sktlim@umich.edu /** Sets the serialization part of this instruction as handled. */ 5622731Sktlim@umich.edu void setSerializeHandled() { status.set(SerializeHandled); } 5632292SN/A 5642292SN/A /** Checks if the serialization part of this instruction has been 5652292SN/A * handled. This does not apply to the temporary serializing 5662292SN/A * state; it only applies to this instruction's own permanent 5672292SN/A * serializing state. 5682292SN/A */ 5692731Sktlim@umich.edu bool isSerializeHandled() { return status[SerializeHandled]; } 5701060SN/A 5711464SN/A /** Returns the opclass of this instruction. */ 5721464SN/A OpClass opClass() const { return staticInst->opClass(); } 5731464SN/A 5741464SN/A /** Returns the branch target address. */ 5751464SN/A Addr branchTarget() const { return staticInst->branchTarget(PC); } 5761464SN/A 5772292SN/A /** Returns the number of source registers. */ 5785543Ssaidi@eecs.umich.edu int8_t numSrcRegs() const { return staticInst->numSrcRegs(); } 5791684SN/A 5802292SN/A /** Returns the number of destination registers. */ 5811060SN/A int8_t numDestRegs() const { return staticInst->numDestRegs(); } 5821060SN/A 5831060SN/A // the following are used to track physical register usage 5841060SN/A // for machines with separate int & FP reg files 5851060SN/A int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); } 5861060SN/A int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); } 5871060SN/A 5881060SN/A /** Returns the logical register index of the i'th destination register. */ 5892292SN/A RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); } 5901060SN/A 5911060SN/A /** Returns the logical register index of the i'th source register. */ 5922292SN/A RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); } 5931060SN/A 5941684SN/A /** Returns the result of an integer instruction. */ 5951464SN/A uint64_t readIntResult() { return instResult.integer; } 5961684SN/A 5971684SN/A /** Returns the result of a floating point instruction. */ 5982356SN/A float readFloatResult() { return (float)instResult.dbl; } 5991684SN/A 6001684SN/A /** Returns the result of a floating point (double) instruction. */ 6011464SN/A double readDoubleResult() { return instResult.dbl; } 6021060SN/A 6032702Sktlim@umich.edu /** Records an integer register being set to a value. */ 6043735Sstever@eecs.umich.edu void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) 6051060SN/A { 6063326Sktlim@umich.edu if (recordResult) 6073326Sktlim@umich.edu instResult.integer = val; 6081060SN/A } 6091060SN/A 6102702Sktlim@umich.edu /** Records an fp register being set to a value. */ 6113735Sstever@eecs.umich.edu void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val, 6123735Sstever@eecs.umich.edu int width) 6132690Sktlim@umich.edu { 6143326Sktlim@umich.edu if (recordResult) { 6153326Sktlim@umich.edu if (width == 32) 6163326Sktlim@umich.edu instResult.dbl = (double)val; 6173326Sktlim@umich.edu else if (width == 64) 6183326Sktlim@umich.edu instResult.dbl = val; 6193326Sktlim@umich.edu else 6203326Sktlim@umich.edu panic("Unsupported width!"); 6213326Sktlim@umich.edu } 6222690Sktlim@umich.edu } 6232690Sktlim@umich.edu 6242702Sktlim@umich.edu /** Records an fp register being set to a value. */ 6253735Sstever@eecs.umich.edu void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 6261060SN/A { 6273326Sktlim@umich.edu if (recordResult) 6283326Sktlim@umich.edu instResult.dbl = (double)val; 6292308SN/A } 6301060SN/A 6312702Sktlim@umich.edu /** Records an fp register being set to an integer value. */ 6323735Sstever@eecs.umich.edu void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val, 6333735Sstever@eecs.umich.edu int width) 6342308SN/A { 6353326Sktlim@umich.edu if (recordResult) 6363326Sktlim@umich.edu instResult.integer = val; 6372308SN/A } 6381060SN/A 6392702Sktlim@umich.edu /** Records an fp register being set to an integer value. */ 6403735Sstever@eecs.umich.edu void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val) 6412308SN/A { 6423326Sktlim@umich.edu if (recordResult) 6433326Sktlim@umich.edu instResult.integer = val; 6441060SN/A } 6451060SN/A 6462190SN/A /** Records that one of the source registers is ready. */ 6472292SN/A void markSrcRegReady(); 6482190SN/A 6492331SN/A /** Marks a specific register as ready. */ 6502292SN/A void markSrcRegReady(RegIndex src_idx); 6512190SN/A 6521684SN/A /** Returns if a source register is ready. */ 6531464SN/A bool isReadySrcRegIdx(int idx) const 6541464SN/A { 6551464SN/A return this->_readySrcRegIdx[idx]; 6561464SN/A } 6571464SN/A 6581684SN/A /** Sets this instruction as completed. */ 6592731Sktlim@umich.edu void setCompleted() { status.set(Completed); } 6601464SN/A 6612292SN/A /** Returns whether or not this instruction is completed. */ 6622731Sktlim@umich.edu bool isCompleted() const { return status[Completed]; } 6631464SN/A 6642731Sktlim@umich.edu /** Marks the result as ready. */ 6652731Sktlim@umich.edu void setResultReady() { status.set(ResultReady); } 6662308SN/A 6672731Sktlim@umich.edu /** Returns whether or not the result is ready. */ 6682731Sktlim@umich.edu bool isResultReady() const { return status[ResultReady]; } 6692308SN/A 6701060SN/A /** Sets this instruction as ready to issue. */ 6712731Sktlim@umich.edu void setCanIssue() { status.set(CanIssue); } 6721060SN/A 6731060SN/A /** Returns whether or not this instruction is ready to issue. */ 6742731Sktlim@umich.edu bool readyToIssue() const { return status[CanIssue]; } 6751060SN/A 6764032Sktlim@umich.edu /** Clears this instruction being able to issue. */ 6774032Sktlim@umich.edu void clearCanIssue() { status.reset(CanIssue); } 6784032Sktlim@umich.edu 6791060SN/A /** Sets this instruction as issued from the IQ. */ 6802731Sktlim@umich.edu void setIssued() { status.set(Issued); } 6811060SN/A 6821060SN/A /** Returns whether or not this instruction has issued. */ 6832731Sktlim@umich.edu bool isIssued() const { return status[Issued]; } 6841060SN/A 6854032Sktlim@umich.edu /** Clears this instruction as being issued. */ 6864032Sktlim@umich.edu void clearIssued() { status.reset(Issued); } 6874032Sktlim@umich.edu 6881060SN/A /** Sets this instruction as executed. */ 6892731Sktlim@umich.edu void setExecuted() { status.set(Executed); } 6901060SN/A 6911060SN/A /** Returns whether or not this instruction has executed. */ 6922731Sktlim@umich.edu bool isExecuted() const { return status[Executed]; } 6931060SN/A 6941060SN/A /** Sets this instruction as ready to commit. */ 6952731Sktlim@umich.edu void setCanCommit() { status.set(CanCommit); } 6961060SN/A 6971061SN/A /** Clears this instruction as being ready to commit. */ 6982731Sktlim@umich.edu void clearCanCommit() { status.reset(CanCommit); } 6991061SN/A 7001060SN/A /** Returns whether or not this instruction is ready to commit. */ 7012731Sktlim@umich.edu bool readyToCommit() const { return status[CanCommit]; } 7022731Sktlim@umich.edu 7032731Sktlim@umich.edu void setAtCommit() { status.set(AtCommit); } 7042731Sktlim@umich.edu 7052731Sktlim@umich.edu bool isAtCommit() { return status[AtCommit]; } 7061060SN/A 7072292SN/A /** Sets this instruction as committed. */ 7082731Sktlim@umich.edu void setCommitted() { status.set(Committed); } 7092292SN/A 7102292SN/A /** Returns whether or not this instruction is committed. */ 7112731Sktlim@umich.edu bool isCommitted() const { return status[Committed]; } 7122292SN/A 7131060SN/A /** Sets this instruction as squashed. */ 7142731Sktlim@umich.edu void setSquashed() { status.set(Squashed); } 7151060SN/A 7161060SN/A /** Returns whether or not this instruction is squashed. */ 7172731Sktlim@umich.edu bool isSquashed() const { return status[Squashed]; } 7181060SN/A 7192292SN/A //Instruction Queue Entry 7202292SN/A //----------------------- 7212292SN/A /** Sets this instruction as a entry the IQ. */ 7222731Sktlim@umich.edu void setInIQ() { status.set(IqEntry); } 7232292SN/A 7242292SN/A /** Sets this instruction as a entry the IQ. */ 7252731Sktlim@umich.edu void clearInIQ() { status.reset(IqEntry); } 7262731Sktlim@umich.edu 7272731Sktlim@umich.edu /** Returns whether or not this instruction has issued. */ 7282731Sktlim@umich.edu bool isInIQ() const { return status[IqEntry]; } 7292292SN/A 7301060SN/A /** Sets this instruction as squashed in the IQ. */ 7312731Sktlim@umich.edu void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);} 7321060SN/A 7331060SN/A /** Returns whether or not this instruction is squashed in the IQ. */ 7342731Sktlim@umich.edu bool isSquashedInIQ() const { return status[SquashedInIQ]; } 7352292SN/A 7362292SN/A 7372292SN/A //Load / Store Queue Functions 7382292SN/A //----------------------- 7392292SN/A /** Sets this instruction as a entry the LSQ. */ 7402731Sktlim@umich.edu void setInLSQ() { status.set(LsqEntry); } 7412292SN/A 7422292SN/A /** Sets this instruction as a entry the LSQ. */ 7432731Sktlim@umich.edu void removeInLSQ() { status.reset(LsqEntry); } 7442731Sktlim@umich.edu 7452731Sktlim@umich.edu /** Returns whether or not this instruction is in the LSQ. */ 7462731Sktlim@umich.edu bool isInLSQ() const { return status[LsqEntry]; } 7472292SN/A 7482292SN/A /** Sets this instruction as squashed in the LSQ. */ 7492731Sktlim@umich.edu void setSquashedInLSQ() { status.set(SquashedInLSQ);} 7502292SN/A 7512292SN/A /** Returns whether or not this instruction is squashed in the LSQ. */ 7522731Sktlim@umich.edu bool isSquashedInLSQ() const { return status[SquashedInLSQ]; } 7532292SN/A 7542292SN/A 7552292SN/A //Reorder Buffer Functions 7562292SN/A //----------------------- 7572292SN/A /** Sets this instruction as a entry the ROB. */ 7582731Sktlim@umich.edu void setInROB() { status.set(RobEntry); } 7592292SN/A 7602292SN/A /** Sets this instruction as a entry the ROB. */ 7612731Sktlim@umich.edu void clearInROB() { status.reset(RobEntry); } 7622731Sktlim@umich.edu 7632731Sktlim@umich.edu /** Returns whether or not this instruction is in the ROB. */ 7642731Sktlim@umich.edu bool isInROB() const { return status[RobEntry]; } 7652292SN/A 7662292SN/A /** Sets this instruction as squashed in the ROB. */ 7672731Sktlim@umich.edu void setSquashedInROB() { status.set(SquashedInROB); } 7682292SN/A 7692292SN/A /** Returns whether or not this instruction is squashed in the ROB. */ 7702731Sktlim@umich.edu bool isSquashedInROB() const { return status[SquashedInROB]; } 7712292SN/A 7721060SN/A /** Read the PC of this instruction. */ 7731464SN/A const Addr readPC() const { return PC; } 7741060SN/A 7754636Sgblack@eecs.umich.edu /**Read the micro PC of this instruction. */ 7764636Sgblack@eecs.umich.edu const Addr readMicroPC() const { return microPC; } 7774636Sgblack@eecs.umich.edu 7781060SN/A /** Set the next PC of this instruction (its actual target). */ 7794636Sgblack@eecs.umich.edu void setNextPC(Addr val) 7802308SN/A { 7812308SN/A nextPC = val; 7822308SN/A } 7832190SN/A 7842935Sksewell@umich.edu /** Set the next NPC of this instruction (the target in Mips or Sparc).*/ 7854636Sgblack@eecs.umich.edu void setNextNPC(Addr val) 7862935Sksewell@umich.edu { 7874632Sgblack@eecs.umich.edu#if ISA_HAS_DELAY_SLOT 7882935Sksewell@umich.edu nextNPC = val; 7894632Sgblack@eecs.umich.edu#endif 7902935Sksewell@umich.edu } 7912935Sksewell@umich.edu 7924636Sgblack@eecs.umich.edu void setNextMicroPC(Addr val) 7934636Sgblack@eecs.umich.edu { 7944636Sgblack@eecs.umich.edu nextMicroPC = val; 7954636Sgblack@eecs.umich.edu } 7964636Sgblack@eecs.umich.edu 7972702Sktlim@umich.edu /** Sets the ASID. */ 7982292SN/A void setASID(short addr_space_id) { asid = addr_space_id; } 7992292SN/A 8002702Sktlim@umich.edu /** Sets the thread id. */ 8016221Snate@binkert.org void setTid(ThreadID tid) { threadNumber = tid; } 8022292SN/A 8032731Sktlim@umich.edu /** Sets the pointer to the thread state. */ 8042702Sktlim@umich.edu void setThreadState(ImplState *state) { thread = state; } 8051060SN/A 8062731Sktlim@umich.edu /** Returns the thread context. */ 8072680Sktlim@umich.edu ThreadContext *tcBase() { return thread->getTC(); } 8081464SN/A 8091464SN/A private: 8101684SN/A /** Instruction effective address. 8111684SN/A * @todo: Consider if this is necessary or not. 8121684SN/A */ 8131464SN/A Addr instEffAddr; 8142292SN/A 8151684SN/A /** Whether or not the effective address calculation is completed. 8161684SN/A * @todo: Consider if this is necessary or not. 8171684SN/A */ 8181464SN/A bool eaCalcDone; 8191464SN/A 8204032Sktlim@umich.edu /** Is this instruction's memory access uncacheable. */ 8214032Sktlim@umich.edu bool isUncacheable; 8224032Sktlim@umich.edu 8234032Sktlim@umich.edu /** Has this instruction generated a memory request. */ 8244032Sktlim@umich.edu bool reqMade; 8254032Sktlim@umich.edu 8261464SN/A public: 8271684SN/A /** Sets the effective address. */ 8281464SN/A void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; } 8291684SN/A 8301684SN/A /** Returns the effective address. */ 8311464SN/A const Addr &getEA() const { return instEffAddr; } 8321684SN/A 8331684SN/A /** Returns whether or not the eff. addr. calculation has been completed. */ 8341464SN/A bool doneEACalc() { return eaCalcDone; } 8351684SN/A 8361684SN/A /** Returns whether or not the eff. addr. source registers are ready. */ 8371464SN/A bool eaSrcsReady(); 8381681SN/A 8392292SN/A /** Whether or not the memory operation is done. */ 8402292SN/A bool memOpDone; 8412292SN/A 8424032Sktlim@umich.edu /** Is this instruction's memory access uncacheable. */ 8434032Sktlim@umich.edu bool uncacheable() { return isUncacheable; } 8444032Sktlim@umich.edu 8454032Sktlim@umich.edu /** Has this instruction generated a memory request. */ 8464032Sktlim@umich.edu bool hasRequest() { return reqMade; } 8474032Sktlim@umich.edu 8481681SN/A public: 8491684SN/A /** Load queue index. */ 8501681SN/A int16_t lqIdx; 8511684SN/A 8521684SN/A /** Store queue index. */ 8531681SN/A int16_t sqIdx; 8542292SN/A 8552292SN/A /** Iterator pointing to this BaseDynInst in the list of all insts. */ 8562292SN/A ListIt instListIt; 8572292SN/A 8582292SN/A /** Returns iterator to this instruction in the list of all insts. */ 8592292SN/A ListIt &getInstListIt() { return instListIt; } 8602292SN/A 8612292SN/A /** Sets iterator for this instruction in the list of all insts. */ 8622292SN/A void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; } 8633326Sktlim@umich.edu 8643326Sktlim@umich.edu public: 8653326Sktlim@umich.edu /** Returns the number of consecutive store conditional failures. */ 8663326Sktlim@umich.edu unsigned readStCondFailures() 8673326Sktlim@umich.edu { return thread->storeCondFailures; } 8683326Sktlim@umich.edu 8693326Sktlim@umich.edu /** Sets the number of consecutive store conditional failures. */ 8703326Sktlim@umich.edu void setStCondFailures(unsigned sc_failures) 8713326Sktlim@umich.edu { thread->storeCondFailures = sc_failures; } 8721060SN/A}; 8731060SN/A 8741060SN/Atemplate<class Impl> 8757520Sgblack@eecs.umich.eduFault 8767520Sgblack@eecs.umich.eduBaseDynInst<Impl>::readBytes(Addr addr, uint8_t *data, 8777520Sgblack@eecs.umich.edu unsigned size, unsigned flags) 8781060SN/A{ 8794032Sktlim@umich.edu reqMade = true; 8807520Sgblack@eecs.umich.edu Request *req = new Request(asid, addr, size, flags, this->PC, 8816429Ssteve.reinhardt@amd.com thread->contextId(), threadNumber); 8822292SN/A 8836974Stjones1@inf.ed.ac.uk Request *sreqLow = NULL; 8846974Stjones1@inf.ed.ac.uk Request *sreqHigh = NULL; 8856974Stjones1@inf.ed.ac.uk 8866974Stjones1@inf.ed.ac.uk // Only split the request if the ISA supports unaligned accesses. 8876974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc) { 8886974Stjones1@inf.ed.ac.uk splitRequest(req, sreqLow, sreqHigh); 8896974Stjones1@inf.ed.ac.uk } 8906974Stjones1@inf.ed.ac.uk initiateTranslation(req, sreqLow, sreqHigh, NULL, BaseTLB::Read); 8914032Sktlim@umich.edu 8922678Sktlim@umich.edu if (fault == NoFault) { 8932678Sktlim@umich.edu effAddr = req->getVaddr(); 8944032Sktlim@umich.edu effAddrValid = true; 8956975Stjones1@inf.ed.ac.uk fault = cpu->read(req, sreqLow, sreqHigh, data, lqIdx); 8966973Stjones1@inf.ed.ac.uk } else { 8972292SN/A // Commit will have to clean up whatever happened. Set this 8982292SN/A // instruction as executed. 8992292SN/A this->setExecuted(); 9001060SN/A } 9011060SN/A 9027577SAli.Saidi@ARM.com if (fault != NoFault) { 9037577SAli.Saidi@ARM.com // Return a fixed value to keep simulation deterministic even 9047577SAli.Saidi@ARM.com // along misspeculated paths. 9057577SAli.Saidi@ARM.com bzero(data, size); 9067577SAli.Saidi@ARM.com } 9077577SAli.Saidi@ARM.com 9081060SN/A if (traceData) { 9091060SN/A traceData->setAddr(addr); 9101060SN/A } 9111060SN/A 9121060SN/A return fault; 9131060SN/A} 9141060SN/A 9151060SN/Atemplate<class Impl> 9161060SN/Atemplate<class T> 9172132SN/Ainline Fault 9187520Sgblack@eecs.umich.eduBaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags) 9197520Sgblack@eecs.umich.edu{ 9207520Sgblack@eecs.umich.edu Fault fault = readBytes(addr, (uint8_t *)&data, sizeof(T), flags); 9217520Sgblack@eecs.umich.edu 9227520Sgblack@eecs.umich.edu data = TheISA::gtoh(data); 9237520Sgblack@eecs.umich.edu 9247520Sgblack@eecs.umich.edu if (traceData) { 9257520Sgblack@eecs.umich.edu traceData->setData(data); 9267520Sgblack@eecs.umich.edu } 9277520Sgblack@eecs.umich.edu 9287520Sgblack@eecs.umich.edu return fault; 9297520Sgblack@eecs.umich.edu} 9307520Sgblack@eecs.umich.edu 9317520Sgblack@eecs.umich.edutemplate<class Impl> 9327520Sgblack@eecs.umich.eduFault 9337520Sgblack@eecs.umich.eduBaseDynInst<Impl>::writeBytes(uint8_t *data, unsigned size, 9347520Sgblack@eecs.umich.edu Addr addr, unsigned flags, uint64_t *res) 9351060SN/A{ 9361060SN/A if (traceData) { 9371060SN/A traceData->setAddr(addr); 9381060SN/A } 9391060SN/A 9404032Sktlim@umich.edu reqMade = true; 9417520Sgblack@eecs.umich.edu Request *req = new Request(asid, addr, size, flags, this->PC, 9426429Ssteve.reinhardt@amd.com thread->contextId(), threadNumber); 9431060SN/A 9446974Stjones1@inf.ed.ac.uk Request *sreqLow = NULL; 9456974Stjones1@inf.ed.ac.uk Request *sreqHigh = NULL; 9466974Stjones1@inf.ed.ac.uk 9476974Stjones1@inf.ed.ac.uk // Only split the request if the ISA supports unaligned accesses. 9486974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc) { 9496974Stjones1@inf.ed.ac.uk splitRequest(req, sreqLow, sreqHigh); 9506974Stjones1@inf.ed.ac.uk } 9516974Stjones1@inf.ed.ac.uk initiateTranslation(req, sreqLow, sreqHigh, res, BaseTLB::Write); 9524032Sktlim@umich.edu 9532090SN/A if (fault == NoFault) { 9542678Sktlim@umich.edu effAddr = req->getVaddr(); 9554032Sktlim@umich.edu effAddrValid = true; 9566975Stjones1@inf.ed.ac.uk fault = cpu->write(req, sreqLow, sreqHigh, data, sqIdx); 9571060SN/A } 9581060SN/A 9591060SN/A return fault; 9601060SN/A} 9611060SN/A 9626973Stjones1@inf.ed.ac.uktemplate<class Impl> 9637520Sgblack@eecs.umich.edutemplate<class T> 9647520Sgblack@eecs.umich.eduinline Fault 9657520Sgblack@eecs.umich.eduBaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res) 9667520Sgblack@eecs.umich.edu{ 9677520Sgblack@eecs.umich.edu if (traceData) { 9687520Sgblack@eecs.umich.edu traceData->setData(data); 9697520Sgblack@eecs.umich.edu } 9707520Sgblack@eecs.umich.edu data = TheISA::htog(data); 9717520Sgblack@eecs.umich.edu return writeBytes((uint8_t *)&data, sizeof(T), addr, flags, res); 9727520Sgblack@eecs.umich.edu} 9737520Sgblack@eecs.umich.edu 9747520Sgblack@eecs.umich.edutemplate<class Impl> 9756973Stjones1@inf.ed.ac.ukinline void 9766974Stjones1@inf.ed.ac.ukBaseDynInst<Impl>::splitRequest(RequestPtr req, RequestPtr &sreqLow, 9776974Stjones1@inf.ed.ac.uk RequestPtr &sreqHigh) 9786974Stjones1@inf.ed.ac.uk{ 9796974Stjones1@inf.ed.ac.uk // Check to see if the request crosses the next level block boundary. 9806974Stjones1@inf.ed.ac.uk unsigned block_size = cpu->getDcachePort()->peerBlockSize(); 9816974Stjones1@inf.ed.ac.uk Addr addr = req->getVaddr(); 9826974Stjones1@inf.ed.ac.uk Addr split_addr = roundDown(addr + req->getSize() - 1, block_size); 9836974Stjones1@inf.ed.ac.uk assert(split_addr <= addr || split_addr - addr < block_size); 9846974Stjones1@inf.ed.ac.uk 9856974Stjones1@inf.ed.ac.uk // Spans two blocks. 9866974Stjones1@inf.ed.ac.uk if (split_addr > addr) { 9876974Stjones1@inf.ed.ac.uk req->splitOnVaddr(split_addr, sreqLow, sreqHigh); 9886974Stjones1@inf.ed.ac.uk } 9896974Stjones1@inf.ed.ac.uk} 9906974Stjones1@inf.ed.ac.uk 9916974Stjones1@inf.ed.ac.uktemplate<class Impl> 9926974Stjones1@inf.ed.ac.ukinline void 9936974Stjones1@inf.ed.ac.ukBaseDynInst<Impl>::initiateTranslation(RequestPtr req, RequestPtr sreqLow, 9946974Stjones1@inf.ed.ac.uk RequestPtr sreqHigh, uint64_t *res, 9956973Stjones1@inf.ed.ac.uk BaseTLB::Mode mode) 9966973Stjones1@inf.ed.ac.uk{ 9976974Stjones1@inf.ed.ac.uk if (!TheISA::HasUnalignedMemAcc || sreqLow == NULL) { 9986974Stjones1@inf.ed.ac.uk WholeTranslationState *state = 9996974Stjones1@inf.ed.ac.uk new WholeTranslationState(req, NULL, res, mode); 10006974Stjones1@inf.ed.ac.uk 10016974Stjones1@inf.ed.ac.uk // One translation if the request isn't split. 10026974Stjones1@inf.ed.ac.uk DataTranslation<BaseDynInst<Impl> > *trans = 10036974Stjones1@inf.ed.ac.uk new DataTranslation<BaseDynInst<Impl> >(this, state); 10046974Stjones1@inf.ed.ac.uk cpu->dtb->translateTiming(req, thread->getTC(), trans, mode); 10056974Stjones1@inf.ed.ac.uk } else { 10066974Stjones1@inf.ed.ac.uk WholeTranslationState *state = 10076974Stjones1@inf.ed.ac.uk new WholeTranslationState(req, sreqLow, sreqHigh, NULL, res, mode); 10086974Stjones1@inf.ed.ac.uk 10096974Stjones1@inf.ed.ac.uk // Two translations when the request is split. 10106974Stjones1@inf.ed.ac.uk DataTranslation<BaseDynInst<Impl> > *stransLow = 10116974Stjones1@inf.ed.ac.uk new DataTranslation<BaseDynInst<Impl> >(this, state, 0); 10126974Stjones1@inf.ed.ac.uk DataTranslation<BaseDynInst<Impl> > *stransHigh = 10136974Stjones1@inf.ed.ac.uk new DataTranslation<BaseDynInst<Impl> >(this, state, 1); 10146974Stjones1@inf.ed.ac.uk 10156974Stjones1@inf.ed.ac.uk cpu->dtb->translateTiming(sreqLow, thread->getTC(), stransLow, mode); 10166974Stjones1@inf.ed.ac.uk cpu->dtb->translateTiming(sreqHigh, thread->getTC(), stransHigh, mode); 10176974Stjones1@inf.ed.ac.uk } 10186973Stjones1@inf.ed.ac.uk} 10196973Stjones1@inf.ed.ac.uk 10206973Stjones1@inf.ed.ac.uktemplate<class Impl> 10216973Stjones1@inf.ed.ac.ukinline void 10226973Stjones1@inf.ed.ac.ukBaseDynInst<Impl>::finishTranslation(WholeTranslationState *state) 10236973Stjones1@inf.ed.ac.uk{ 10246973Stjones1@inf.ed.ac.uk fault = state->getFault(); 10256973Stjones1@inf.ed.ac.uk 10266973Stjones1@inf.ed.ac.uk if (state->isUncacheable()) 10276973Stjones1@inf.ed.ac.uk isUncacheable = true; 10286973Stjones1@inf.ed.ac.uk 10296973Stjones1@inf.ed.ac.uk if (fault == NoFault) { 10306973Stjones1@inf.ed.ac.uk physEffAddr = state->getPaddr(); 10316973Stjones1@inf.ed.ac.uk memReqFlags = state->getFlags(); 10326973Stjones1@inf.ed.ac.uk 10336973Stjones1@inf.ed.ac.uk if (state->mainReq->isCondSwap()) { 10346973Stjones1@inf.ed.ac.uk assert(state->res); 10356973Stjones1@inf.ed.ac.uk state->mainReq->setExtraData(*state->res); 10366973Stjones1@inf.ed.ac.uk } 10376973Stjones1@inf.ed.ac.uk 10386973Stjones1@inf.ed.ac.uk } else { 10396973Stjones1@inf.ed.ac.uk state->deleteReqs(); 10406973Stjones1@inf.ed.ac.uk } 10416973Stjones1@inf.ed.ac.uk delete state; 10426973Stjones1@inf.ed.ac.uk} 10436973Stjones1@inf.ed.ac.uk 10441464SN/A#endif // __CPU_BASE_DYN_INST_HH__ 1045