base.hh revision 56 
1/*
2 * Copyright (c) 2003 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __BASE_CPU_HH__
30#define __BASE_CPU_HH__
31
32#include <vector>
33
34#include "sim/eventq.hh"
35#include "sim/sim_object.hh"
36
37#include "targetarch/isa_traits.hh"	// for Addr
38
39#ifdef FULL_SYSTEM
40class System;
41#endif
42
43class BranchPred;
44class ExecContext;
45
46class BaseCPU : public SimObject
47{
48#ifdef FULL_SYSTEM
49  protected:
50    int number;
51    Tick frequency;
52    uint8_t interrupts[NumInterruptLevels];
53    uint64_t intstatus;
54
55  public:
56    virtual void post_interrupt(int int_num, int index);
57    virtual void clear_interrupt(int int_num, int index);
58    virtual void clear_interrupts();
59
60    bool check_interrupt(int int_num) const {
61        if (int_num > NumInterruptLevels)
62            panic("int_num out of bounds\n");
63
64        return interrupts[int_num] != 0;
65    }
66
67    bool check_interrupts() const { return intstatus != 0; }
68    uint64_t intr_status() const { return intstatus; }
69
70    Tick getFreq() const { return frequency; }
71#endif
72
73  protected:
74    std::vector<ExecContext *> contexts;
75
76  public:
77    virtual void execCtxStatusChg() {}
78
79  public:
80
81#ifdef FULL_SYSTEM
82    BaseCPU(const std::string &_name, int _number_of_threads,
83            Counter max_insts_any_thread, Counter max_insts_all_threads,
84            System *_system,
85            int num, Tick freq);
86#else
87    BaseCPU(const std::string &_name, int _number_of_threads,
88            Counter max_insts_any_thread = 0,
89            Counter max_insts_all_threads = 0);
90#endif
91
92    virtual ~BaseCPU() {}
93
94    virtual void regStats();
95
96    /// Number of threads we're actually simulating (<= SMT_MAX_THREADS).
97    /// This is a constant for the duration of the simulation.
98    int number_of_threads;
99
100    /// Vector of per-thread instruction-based event queues.  Used for
101    /// scheduling events based on number of instructions committed by
102    /// a particular thread.
103    EventQueue **comInsnEventQueue;
104
105#ifdef FULL_SYSTEM
106    System *system;
107#endif
108
109    virtual bool filterThisInstructionPrefetch(int thread_number,
110        short asid, Addr prefetchTarget) const { return true; }
111
112    /// Return pointer to CPU's branch predictor (NULL if none).
113    virtual BranchPred *getBranchPred() { return NULL; };
114
115  private:
116    static std::vector<BaseCPU *> cpuList;   //!< Static global cpu list
117
118  public:
119    static int numSimulatedCPUs() { return cpuList.size(); }
120};
121
122#endif // __BASE_CPU_HH__
123