base.hh revision 56
15086Sgblack@eecs.umich.edu/* 25086Sgblack@eecs.umich.edu * Copyright (c) 2003 The Regents of The University of Michigan 35086Sgblack@eecs.umich.edu * All rights reserved. 45086Sgblack@eecs.umich.edu * 55086Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 65086Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 75086Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 85086Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 95086Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 105086Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 115086Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 125086Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 135086Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 145086Sgblack@eecs.umich.edu * this software without specific prior written permission. 155086Sgblack@eecs.umich.edu * 165086Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 175086Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 185086Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 195086Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 205086Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 215086Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 225086Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 235086Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 245086Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 255086Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 265086Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 275086Sgblack@eecs.umich.edu */ 285086Sgblack@eecs.umich.edu 295086Sgblack@eecs.umich.edu#ifndef __BASE_CPU_HH__ 305086Sgblack@eecs.umich.edu#define __BASE_CPU_HH__ 315086Sgblack@eecs.umich.edu 325086Sgblack@eecs.umich.edu#include <vector> 335086Sgblack@eecs.umich.edu 345086Sgblack@eecs.umich.edu#include "sim/eventq.hh" 355086Sgblack@eecs.umich.edu#include "sim/sim_object.hh" 365086Sgblack@eecs.umich.edu 375086Sgblack@eecs.umich.edu#include "targetarch/isa_traits.hh" // for Addr 385086Sgblack@eecs.umich.edu 395086Sgblack@eecs.umich.edu#ifdef FULL_SYSTEM 408706Sandreas.hansson@arm.comclass System; 415086Sgblack@eecs.umich.edu#endif 425086Sgblack@eecs.umich.edu 435086Sgblack@eecs.umich.educlass BranchPred; 445086Sgblack@eecs.umich.educlass ExecContext; 455086Sgblack@eecs.umich.edu 465086Sgblack@eecs.umich.educlass BaseCPU : public SimObject 475086Sgblack@eecs.umich.edu{ 485086Sgblack@eecs.umich.edu#ifdef FULL_SYSTEM 495086Sgblack@eecs.umich.edu protected: 505086Sgblack@eecs.umich.edu int number; 518852Sandreas.hansson@arm.com Tick frequency; 525086Sgblack@eecs.umich.edu uint8_t interrupts[NumInterruptLevels]; 535086Sgblack@eecs.umich.edu uint64_t intstatus; 545086Sgblack@eecs.umich.edu 558852Sandreas.hansson@arm.com public: 565086Sgblack@eecs.umich.edu virtual void post_interrupt(int int_num, int index); 575086Sgblack@eecs.umich.edu virtual void clear_interrupt(int int_num, int index); 585086Sgblack@eecs.umich.edu virtual void clear_interrupts(); 598852Sandreas.hansson@arm.com 605086Sgblack@eecs.umich.edu bool check_interrupt(int int_num) const { 615086Sgblack@eecs.umich.edu if (int_num > NumInterruptLevels) 625086Sgblack@eecs.umich.edu panic("int_num out of bounds\n"); 638852Sandreas.hansson@arm.com 645086Sgblack@eecs.umich.edu return interrupts[int_num] != 0; 655086Sgblack@eecs.umich.edu } 665086Sgblack@eecs.umich.edu 678852Sandreas.hansson@arm.com bool check_interrupts() const { return intstatus != 0; } 685086Sgblack@eecs.umich.edu uint64_t intr_status() const { return intstatus; } 695086Sgblack@eecs.umich.edu 705086Sgblack@eecs.umich.edu Tick getFreq() const { return frequency; } 718852Sandreas.hansson@arm.com#endif 725086Sgblack@eecs.umich.edu 735086Sgblack@eecs.umich.edu protected: 745086Sgblack@eecs.umich.edu std::vector<ExecContext *> contexts; 755086Sgblack@eecs.umich.edu 765086Sgblack@eecs.umich.edu public: 775086Sgblack@eecs.umich.edu virtual void execCtxStatusChg() {} 785086Sgblack@eecs.umich.edu 795086Sgblack@eecs.umich.edu public: 805086Sgblack@eecs.umich.edu 815086Sgblack@eecs.umich.edu#ifdef FULL_SYSTEM 825086Sgblack@eecs.umich.edu BaseCPU(const std::string &_name, int _number_of_threads, 838852Sandreas.hansson@arm.com Counter max_insts_any_thread, Counter max_insts_all_threads, 848852Sandreas.hansson@arm.com System *_system, 855086Sgblack@eecs.umich.edu int num, Tick freq); 865086Sgblack@eecs.umich.edu#else 875086Sgblack@eecs.umich.edu BaseCPU(const std::string &_name, int _number_of_threads, 885086Sgblack@eecs.umich.edu Counter max_insts_any_thread = 0, 895086Sgblack@eecs.umich.edu Counter max_insts_all_threads = 0); 905086Sgblack@eecs.umich.edu#endif 915086Sgblack@eecs.umich.edu 925086Sgblack@eecs.umich.edu virtual ~BaseCPU() {} 935086Sgblack@eecs.umich.edu 945086Sgblack@eecs.umich.edu virtual void regStats(); 955086Sgblack@eecs.umich.edu 965086Sgblack@eecs.umich.edu /// Number of threads we're actually simulating (<= SMT_MAX_THREADS). 975086Sgblack@eecs.umich.edu /// This is a constant for the duration of the simulation. 988852Sandreas.hansson@arm.com int number_of_threads; 998852Sandreas.hansson@arm.com 1005086Sgblack@eecs.umich.edu /// Vector of per-thread instruction-based event queues. Used for 1015086Sgblack@eecs.umich.edu /// scheduling events based on number of instructions committed by 1025086Sgblack@eecs.umich.edu /// a particular thread. 1035086Sgblack@eecs.umich.edu EventQueue **comInsnEventQueue; 1045086Sgblack@eecs.umich.edu 1055086Sgblack@eecs.umich.edu#ifdef FULL_SYSTEM 1065086Sgblack@eecs.umich.edu System *system; 1075086Sgblack@eecs.umich.edu#endif 1085086Sgblack@eecs.umich.edu 1095086Sgblack@eecs.umich.edu virtual bool filterThisInstructionPrefetch(int thread_number, 1105086Sgblack@eecs.umich.edu short asid, Addr prefetchTarget) const { return true; } 1115086Sgblack@eecs.umich.edu 1125086Sgblack@eecs.umich.edu /// Return pointer to CPU's branch predictor (NULL if none). 1135086Sgblack@eecs.umich.edu virtual BranchPred *getBranchPred() { return NULL; }; 1145086Sgblack@eecs.umich.edu 1155086Sgblack@eecs.umich.edu private: 1165086Sgblack@eecs.umich.edu static std::vector<BaseCPU *> cpuList; //!< Static global cpu list 1175086Sgblack@eecs.umich.edu 1185086Sgblack@eecs.umich.edu public: 1195086Sgblack@eecs.umich.edu static int numSimulatedCPUs() { return cpuList.size(); } 1205086Sgblack@eecs.umich.edu}; 1215086Sgblack@eecs.umich.edu 1225086Sgblack@eecs.umich.edu#endif // __BASE_CPU_HH__ 1235086Sgblack@eecs.umich.edu