base.hh revision 503 
1/*
2 * Copyright (c) 2003 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __BASE_CPU_HH__
30#define __BASE_CPU_HH__
31
32#include <vector>
33
34#include "sim/eventq.hh"
35#include "sim/sim_object.hh"
36
37#include "targetarch/isa_traits.hh"	// for Addr
38
39#ifdef FULL_SYSTEM
40class System;
41#endif
42
43class BranchPred;
44class ExecContext;
45
46class BaseCPU : public SimObject
47{
48#ifdef FULL_SYSTEM
49  protected:
50    Tick frequency;
51    uint8_t interrupts[NumInterruptLevels];
52    uint64_t intstatus;
53
54  public:
55    virtual void post_interrupt(int int_num, int index);
56    virtual void clear_interrupt(int int_num, int index);
57    virtual void clear_interrupts();
58
59    bool check_interrupt(int int_num) const {
60        if (int_num > NumInterruptLevels)
61            panic("int_num out of bounds\n");
62
63        return interrupts[int_num] != 0;
64    }
65
66    bool check_interrupts() const { return intstatus != 0; }
67    uint64_t intr_status() const { return intstatus; }
68
69    Tick getFreq() const { return frequency; }
70#endif
71
72  protected:
73    std::vector<ExecContext *> execContexts;
74
75  public:
76
77    /// Notify the CPU that the indicated context is now active.  The
78    /// delay parameter indicates the number of ticks to wait before
79    /// executing (typically 0 or 1).
80    virtual void activateContext(int thread_num, int delay) {}
81
82    /// Notify the CPU that the indicated context is now suspended.
83    virtual void suspendContext(int thread_num) {}
84
85    /// Notify the CPU that the indicated context is now deallocated.
86    virtual void deallocateContext(int thread_num) {}
87
88    /// Notify the CPU that the indicated context is now halted.
89    virtual void haltContext(int thread_num) {}
90
91  public:
92
93#ifdef FULL_SYSTEM
94    BaseCPU(const std::string &_name, int _number_of_threads,
95            Counter max_insts_any_thread, Counter max_insts_all_threads,
96            Counter max_loads_any_thread, Counter max_loads_all_threads,
97            System *_system, Tick freq);
98#else
99    BaseCPU(const std::string &_name, int _number_of_threads,
100            Counter max_insts_any_thread = 0,
101            Counter max_insts_all_threads = 0,
102            Counter max_loads_any_thread = 0,
103            Counter max_loads_all_threads = 0);
104#endif
105
106    virtual ~BaseCPU() {}
107
108    virtual void regStats();
109
110    void registerExecContexts();
111
112    /// Prepare for another CPU to take over execution.  Called by
113    /// takeOverFrom() on its argument.
114    virtual void switchOut();
115
116    /// Take over execution from the given CPU.  Used for warm-up and
117    /// sampling.
118    virtual void takeOverFrom(BaseCPU *);
119
120    /**
121     *  Number of threads we're actually simulating (<= SMT_MAX_THREADS).
122     * This is a constant for the duration of the simulation.
123     */
124    int number_of_threads;
125
126    /**
127     * Vector of per-thread instruction-based event queues.  Used for
128     * scheduling events based on number of instructions committed by
129     * a particular thread.
130     */
131    EventQueue **comInstEventQueue;
132
133    /**
134     * Vector of per-thread load-based event queues.  Used for
135     * scheduling events based on number of loads committed by
136     *a particular thread.
137     */
138    EventQueue **comLoadEventQueue;
139
140#ifdef FULL_SYSTEM
141    System *system;
142#endif
143
144    /**
145     * Return pointer to CPU's branch predictor (NULL if none).
146     * @return Branch predictor pointer.
147     */
148    virtual BranchPred *getBranchPred() { return NULL; };
149
150  private:
151    static std::vector<BaseCPU *> cpuList;   //!< Static global cpu list
152
153  public:
154    static int numSimulatedCPUs() { return cpuList.size(); }
155};
156
157#endif // __BASE_CPU_HH__
158