base.hh revision 503
12810SN/A/* 22810SN/A * Copyright (c) 2003 The Regents of The University of Michigan 32810SN/A * All rights reserved. 42810SN/A * 52810SN/A * Redistribution and use in source and binary forms, with or without 62810SN/A * modification, are permitted provided that the following conditions are 72810SN/A * met: redistributions of source code must retain the above copyright 82810SN/A * notice, this list of conditions and the following disclaimer; 92810SN/A * redistributions in binary form must reproduce the above copyright 102810SN/A * notice, this list of conditions and the following disclaimer in the 112810SN/A * documentation and/or other materials provided with the distribution; 122810SN/A * neither the name of the copyright holders nor the names of its 132810SN/A * contributors may be used to endorse or promote products derived from 142810SN/A * this software without specific prior written permission. 152810SN/A * 162810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242810SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252810SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262810SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272810SN/A */ 282810SN/A 294458SN/A#ifndef __BASE_CPU_HH__ 304458SN/A#define __BASE_CPU_HH__ 312810SN/A 322810SN/A#include <vector> 332810SN/A 342810SN/A#include "sim/eventq.hh" 352810SN/A#include "sim/sim_object.hh" 362810SN/A 372810SN/A#include "targetarch/isa_traits.hh" // for Addr 382810SN/A 392810SN/A#ifdef FULL_SYSTEM 402810SN/Aclass System; 417676Snate@binkert.org#endif 427676Snate@binkert.org 437676Snate@binkert.orgclass BranchPred; 442810SN/Aclass ExecContext; 452810SN/A 462825SN/Aclass BaseCPU : public SimObject 472810SN/A{ 482810SN/A#ifdef FULL_SYSTEM 496215Snate@binkert.org protected: 508232Snate@binkert.org Tick frequency; 518232Snate@binkert.org uint8_t interrupts[NumInterruptLevels]; 525338Sstever@gmail.com uint64_t intstatus; 532810SN/A 542810SN/A public: 558229Snate@binkert.org virtual void post_interrupt(int int_num, int index); 564626SN/A virtual void clear_interrupt(int int_num, int index); 575034SN/A virtual void clear_interrupts(); 582811SN/A 598786Sgblack@eecs.umich.edu bool check_interrupt(int int_num) const { 604626SN/A if (int_num > NumInterruptLevels) 618833Sdam.sunwoo@arm.com panic("int_num out of bounds\n"); 622810SN/A 633194SN/A return interrupts[int_num] != 0; 642810SN/A } 652810SN/A 662810SN/A bool check_interrupts() const { return intstatus != 0; } 672810SN/A uint64_t intr_status() const { return intstatus; } 682810SN/A 694628SN/A Tick getFreq() const { return frequency; } 704628SN/A#endif 714628SN/A 724628SN/A protected: 734628SN/A std::vector<ExecContext *> execContexts; 744628SN/A 754628SN/A public: 764628SN/A 778737Skoansin.tan@gmail.com /// Notify the CPU that the indicated context is now active. The 784628SN/A /// delay parameter indicates the number of ticks to wait before 794628SN/A /// executing (typically 0 or 1). 804628SN/A virtual void activateContext(int thread_num, int delay) {} 814628SN/A 824628SN/A /// Notify the CPU that the indicated context is now suspended. 834628SN/A virtual void suspendContext(int thread_num) {} 844628SN/A 854628SN/A /// Notify the CPU that the indicated context is now deallocated. 864628SN/A virtual void deallocateContext(int thread_num) {} 874628SN/A 884628SN/A /// Notify the CPU that the indicated context is now halted. 894628SN/A virtual void haltContext(int thread_num) {} 904628SN/A 914628SN/A public: 924628SN/A 934628SN/A#ifdef FULL_SYSTEM 944628SN/A BaseCPU(const std::string &_name, int _number_of_threads, 954628SN/A Counter max_insts_any_thread, Counter max_insts_all_threads, 964628SN/A Counter max_loads_any_thread, Counter max_loads_all_threads, 974628SN/A System *_system, Tick freq); 988737Skoansin.tan@gmail.com#else 994628SN/A BaseCPU(const std::string &_name, int _number_of_threads, 1004626SN/A Counter max_insts_any_thread = 0, 1012810SN/A Counter max_insts_all_threads = 0, 1022844SN/A Counter max_loads_any_thread = 0, 1032810SN/A Counter max_loads_all_threads = 0); 1042810SN/A#endif 1053738SN/A 1064965SN/A virtual ~BaseCPU() {} 1076122SSteve.Reinhardt@amd.com 1084458SN/A virtual void regStats(); 1096227Snate@binkert.org 1102810SN/A void registerExecContexts(); 1114458SN/A 1123013SN/A /// Prepare for another CPU to take over execution. Called by 1134666SN/A /// takeOverFrom() on its argument. 1144666SN/A virtual void switchOut(); 1154666SN/A 1165314SN/A /// Take over execution from the given CPU. Used for warm-up and 1175314SN/A /// sampling. 1182811SN/A virtual void takeOverFrom(BaseCPU *); 1192810SN/A 1202810SN/A /** 1212810SN/A * Number of threads we're actually simulating (<= SMT_MAX_THREADS). 1222810SN/A * This is a constant for the duration of the simulation. 1235314SN/A */ 1243606SN/A int number_of_threads; 1252810SN/A 1262810SN/A /** 1272897SN/A * Vector of per-thread instruction-based event queues. Used for 1282897SN/A * scheduling events based on number of instructions committed by 1294458SN/A * a particular thread. 1304458SN/A */ 1314888SN/A EventQueue **comInstEventQueue; 1324666SN/A 1334666SN/A /** 1344458SN/A * Vector of per-thread load-based event queues. Used for 1354458SN/A * scheduling events based on number of loads committed by 1364458SN/A *a particular thread. 1374626SN/A */ 1384626SN/A EventQueue **comLoadEventQueue; 1394626SN/A 1402811SN/A#ifdef FULL_SYSTEM 1412810SN/A System *system; 1423338SN/A#endif 1433738SN/A 1443338SN/A /** 1454626SN/A * Return pointer to CPU's branch predictor (NULL if none). 1464626SN/A * @return Branch predictor pointer. 1474626SN/A */ 1484626SN/A virtual BranchPred *getBranchPred() { return NULL; }; 1494626SN/A 1504626SN/A private: 1514626SN/A static std::vector<BaseCPU *> cpuList; //!< Static global cpu list 1524626SN/A 1534628SN/A public: 1544628SN/A static int numSimulatedCPUs() { return cpuList.size(); } 1554628SN/A}; 1564666SN/A 1574628SN/A#endif // __BASE_CPU_HH__ 1584628SN/A