base.hh revision 4776
12SN/A/* 21762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292665Ssaidi@eecs.umich.edu * Nathan Binkert 302SN/A */ 312SN/A 321717SN/A#ifndef __CPU_BASE_HH__ 331717SN/A#define __CPU_BASE_HH__ 342SN/A 352SN/A#include <vector> 362SN/A 374182Sgblack@eecs.umich.edu#include "arch/isa_traits.hh" 38707SN/A#include "base/statistics.hh" 391858SN/A#include "config/full_system.hh" 4056SN/A#include "sim/eventq.hh" 414776Sgblack@eecs.umich.edu#include "sim/insttracer.hh" 422856Srdreslin@umich.edu#include "mem/mem_object.hh" 432SN/A 443520Sgblack@eecs.umich.edu#if FULL_SYSTEM 453520Sgblack@eecs.umich.edu#include "arch/interrupts.hh" 463520Sgblack@eecs.umich.edu#endif 473520Sgblack@eecs.umich.edu 482190SN/Aclass BranchPred; 492315SN/Aclass CheckerCPU; 502680Sktlim@umich.educlass ThreadContext; 512SN/Aclass System; 522856Srdreslin@umich.educlass Port; 532SN/A 544182Sgblack@eecs.umich.edunamespace TheISA 554182Sgblack@eecs.umich.edu{ 564182Sgblack@eecs.umich.edu class Predecoder; 574182Sgblack@eecs.umich.edu} 584182Sgblack@eecs.umich.edu 592356SN/Aclass CPUProgressEvent : public Event 602356SN/A{ 612356SN/A protected: 622356SN/A Tick interval; 632356SN/A Counter lastNumInst; 642356SN/A BaseCPU *cpu; 652356SN/A 662356SN/A public: 673126Sktlim@umich.edu CPUProgressEvent(EventQueue *q, Tick ival, BaseCPU *_cpu); 682356SN/A 692356SN/A void process(); 702356SN/A 712356SN/A virtual const char *description(); 722356SN/A}; 732356SN/A 742856Srdreslin@umich.educlass BaseCPU : public MemObject 752SN/A{ 761634SN/A protected: 771634SN/A // CPU's clock period in terms of the number of ticks of curTime. 781695SN/A Tick clock; 793814Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 803814Ssaidi@eecs.umich.edu Tick instCnt; 811634SN/A 821634SN/A public: 832359SN/A// Tick currentTick; 841695SN/A inline Tick frequency() const { return Clock::Frequency / clock; } 851695SN/A inline Tick cycles(int numCycles) const { return clock * numCycles; } 861695SN/A inline Tick curCycle() const { return curTick / clock; } 873814Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 883814Ssaidi@eecs.umich.edu Tick instCount() { return instCnt; } 891634SN/A 903495Sktlim@umich.edu /** The next cycle the CPU should be scheduled, given a cache 913495Sktlim@umich.edu * access or quiesce event returning on this cycle. This function 923495Sktlim@umich.edu * may return curTick if the CPU should run on the current cycle. 933495Sktlim@umich.edu */ 943495Sktlim@umich.edu Tick nextCycle(); 953495Sktlim@umich.edu 963495Sktlim@umich.edu /** The next cycle the CPU should be scheduled, given a cache 973495Sktlim@umich.edu * access or quiesce event returning on the given Tick. This 983495Sktlim@umich.edu * function may return curTick if the CPU should run on the 993495Sktlim@umich.edu * current cycle. 1003495Sktlim@umich.edu * @param begin_tick The tick that the event is completing on. 1013495Sktlim@umich.edu */ 1023495Sktlim@umich.edu Tick nextCycle(Tick begin_tick); 1033495Sktlim@umich.edu 1041858SN/A#if FULL_SYSTEM 1052SN/A protected: 1063520Sgblack@eecs.umich.edu// uint64_t interrupts[TheISA::NumInterruptLevels]; 1073520Sgblack@eecs.umich.edu// uint64_t intstatus; 1083520Sgblack@eecs.umich.edu TheISA::Interrupts interrupts; 1092SN/A 1102SN/A public: 1112SN/A virtual void post_interrupt(int int_num, int index); 1122SN/A virtual void clear_interrupt(int int_num, int index); 1132SN/A virtual void clear_interrupts(); 1144103Ssaidi@eecs.umich.edu virtual uint64_t get_interrupts(int int_num); 1152SN/A 1163521Sgblack@eecs.umich.edu bool check_interrupts(ThreadContext * tc) const 1173521Sgblack@eecs.umich.edu { return interrupts.check_interrupts(tc); } 1181917SN/A 1191917SN/A class ProfileEvent : public Event 1201917SN/A { 1211917SN/A private: 1221917SN/A BaseCPU *cpu; 1231917SN/A int interval; 1241917SN/A 1251917SN/A public: 1261917SN/A ProfileEvent(BaseCPU *cpu, int interval); 1271917SN/A void process(); 1281917SN/A }; 1291917SN/A ProfileEvent *profileEvent; 1302SN/A#endif 1312SN/A 1322SN/A protected: 1332680Sktlim@umich.edu std::vector<ThreadContext *> threadContexts; 1344182Sgblack@eecs.umich.edu std::vector<TheISA::Predecoder *> predecoders; 1352SN/A 1364776Sgblack@eecs.umich.edu Trace::InstTracer * tracer; 1374776Sgblack@eecs.umich.edu 1382SN/A public: 139393SN/A 1404776Sgblack@eecs.umich.edu /// Provide access to the tracer pointer 1414776Sgblack@eecs.umich.edu Trace::InstTracer * getTracer() { return tracer; } 1424776Sgblack@eecs.umich.edu 143393SN/A /// Notify the CPU that the indicated context is now active. The 144393SN/A /// delay parameter indicates the number of ticks to wait before 145393SN/A /// executing (typically 0 or 1). 146393SN/A virtual void activateContext(int thread_num, int delay) {} 147393SN/A 148393SN/A /// Notify the CPU that the indicated context is now suspended. 149393SN/A virtual void suspendContext(int thread_num) {} 150393SN/A 151393SN/A /// Notify the CPU that the indicated context is now deallocated. 152393SN/A virtual void deallocateContext(int thread_num) {} 153393SN/A 154393SN/A /// Notify the CPU that the indicated context is now halted. 155393SN/A virtual void haltContext(int thread_num) {} 1562SN/A 1574000Ssaidi@eecs.umich.edu /// Given a Thread Context pointer return the thread num 1584000Ssaidi@eecs.umich.edu int findContext(ThreadContext *tc); 1594000Ssaidi@eecs.umich.edu 1604000Ssaidi@eecs.umich.edu /// Given a thread num get tho thread context for it 1614000Ssaidi@eecs.umich.edu ThreadContext *getContext(int tn) { return threadContexts[tn]; } 1624000Ssaidi@eecs.umich.edu 1632SN/A public: 1641400SN/A struct Params 1651400SN/A { 1661400SN/A std::string name; 1671400SN/A int numberOfThreads; 1681400SN/A bool deferRegistration; 1691400SN/A Counter max_insts_any_thread; 1701400SN/A Counter max_insts_all_threads; 1711400SN/A Counter max_loads_any_thread; 1721400SN/A Counter max_loads_all_threads; 1731695SN/A Tick clock; 1741400SN/A bool functionTrace; 1751400SN/A Tick functionTraceStart; 1762378SN/A System *system; 1773170Sstever@eecs.umich.edu int cpu_id; 1784776Sgblack@eecs.umich.edu Trace::InstTracer * tracer; 1794776Sgblack@eecs.umich.edu 1803661Srdreslin@umich.edu Tick phase; 1811858SN/A#if FULL_SYSTEM 1821917SN/A Tick profile; 1833617Sbinkertn@umich.edu 1843617Sbinkertn@umich.edu bool do_statistics_insts; 1853617Sbinkertn@umich.edu bool do_checkpoint_insts; 1863617Sbinkertn@umich.edu bool do_quiesce; 1871400SN/A#endif 1882356SN/A Tick progress_interval; 1892315SN/A BaseCPU *checker; 1901917SN/A 1911917SN/A Params(); 1921400SN/A }; 1932SN/A 1941400SN/A const Params *params; 1952SN/A 1961400SN/A BaseCPU(Params *params); 1971191SN/A virtual ~BaseCPU(); 1982SN/A 1991129SN/A virtual void init(); 2001917SN/A virtual void startup(); 2012SN/A virtual void regStats(); 2022SN/A 2032103SN/A virtual void activateWhenReady(int tid) {}; 2042103SN/A 2052680Sktlim@umich.edu void registerThreadContexts(); 206180SN/A 2071492SN/A /// Prepare for another CPU to take over execution. When it is 2081492SN/A /// is ready (drained pipe) it signals the sampler. 2092798Sktlim@umich.edu virtual void switchOut(); 210180SN/A 211180SN/A /// Take over execution from the given CPU. Used for warm-up and 212180SN/A /// sampling. 2134192Sktlim@umich.edu virtual void takeOverFrom(BaseCPU *, Port *ic, Port *dc); 214180SN/A 215124SN/A /** 216124SN/A * Number of threads we're actually simulating (<= SMT_MAX_THREADS). 217124SN/A * This is a constant for the duration of the simulation. 218124SN/A */ 2192SN/A int number_of_threads; 2202SN/A 221124SN/A /** 222124SN/A * Vector of per-thread instruction-based event queues. Used for 223124SN/A * scheduling events based on number of instructions committed by 224124SN/A * a particular thread. 225124SN/A */ 226503SN/A EventQueue **comInstEventQueue; 2272SN/A 228124SN/A /** 229124SN/A * Vector of per-thread load-based event queues. Used for 230124SN/A * scheduling events based on number of loads committed by 231124SN/A *a particular thread. 232124SN/A */ 233124SN/A EventQueue **comLoadEventQueue; 234124SN/A 2352SN/A System *system; 236921SN/A 2373661Srdreslin@umich.edu Tick phase; 2383661Srdreslin@umich.edu 2392378SN/A#if FULL_SYSTEM 240921SN/A /** 241921SN/A * Serialize this object to the given output stream. 242921SN/A * @param os The stream to serialize to. 243921SN/A */ 244921SN/A virtual void serialize(std::ostream &os); 245921SN/A 246921SN/A /** 247921SN/A * Reconstruct the state of this object from a checkpoint. 248921SN/A * @param cp The checkpoint use. 249921SN/A * @param section The section name of this object 250921SN/A */ 251921SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion); 252921SN/A 2532SN/A#endif 2542SN/A 255124SN/A /** 256124SN/A * Return pointer to CPU's branch predictor (NULL if none). 257124SN/A * @return Branch predictor pointer. 258124SN/A */ 2592SN/A virtual BranchPred *getBranchPred() { return NULL; }; 2602SN/A 261707SN/A virtual Counter totalInstructions() const { return 0; } 262707SN/A 2631191SN/A // Function tracing 2641191SN/A private: 2651191SN/A bool functionTracingEnabled; 2661191SN/A std::ostream *functionTraceStream; 2671191SN/A Addr currentFunctionStart; 2681191SN/A Addr currentFunctionEnd; 2691191SN/A Tick functionEntryTick; 2701191SN/A void enableFunctionTrace(); 2711191SN/A void traceFunctionsInternal(Addr pc); 2721191SN/A 2731191SN/A protected: 2741191SN/A void traceFunctions(Addr pc) 2751191SN/A { 2761191SN/A if (functionTracingEnabled) 2771191SN/A traceFunctionsInternal(pc); 2781191SN/A } 2791191SN/A 2802SN/A private: 2812SN/A static std::vector<BaseCPU *> cpuList; //!< Static global cpu list 2822SN/A 2832SN/A public: 2842SN/A static int numSimulatedCPUs() { return cpuList.size(); } 285707SN/A static Counter numSimulatedInstructions() 286707SN/A { 287707SN/A Counter total = 0; 288707SN/A 289707SN/A int size = cpuList.size(); 290707SN/A for (int i = 0; i < size; ++i) 291707SN/A total += cpuList[i]->totalInstructions(); 292707SN/A 293707SN/A return total; 294707SN/A } 295707SN/A 296707SN/A public: 297707SN/A // Number of CPU cycles simulated 298729SN/A Stats::Scalar<> numCycles; 2992SN/A}; 3002SN/A 3011717SN/A#endif // __CPU_BASE_HH__ 302