base.hh revision 4776 
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 *          Nathan Binkert
30 */
31
32#ifndef __CPU_BASE_HH__
33#define __CPU_BASE_HH__
34
35#include <vector>
36
37#include "arch/isa_traits.hh"
38#include "base/statistics.hh"
39#include "config/full_system.hh"
40#include "sim/eventq.hh"
41#include "sim/insttracer.hh"
42#include "mem/mem_object.hh"
43
44#if FULL_SYSTEM
45#include "arch/interrupts.hh"
46#endif
47
48class BranchPred;
49class CheckerCPU;
50class ThreadContext;
51class System;
52class Port;
53
54namespace TheISA
55{
56    class Predecoder;
57}
58
59class CPUProgressEvent : public Event
60{
61  protected:
62    Tick interval;
63    Counter lastNumInst;
64    BaseCPU *cpu;
65
66  public:
67    CPUProgressEvent(EventQueue *q, Tick ival, BaseCPU *_cpu);
68
69    void process();
70
71    virtual const char *description();
72};
73
74class BaseCPU : public MemObject
75{
76  protected:
77    // CPU's clock period in terms of the number of ticks of curTime.
78    Tick clock;
79    // @todo remove me after debugging with legion done
80    Tick instCnt;
81
82  public:
83//    Tick currentTick;
84    inline Tick frequency() const { return Clock::Frequency / clock; }
85    inline Tick cycles(int numCycles) const { return clock * numCycles; }
86    inline Tick curCycle() const { return curTick / clock; }
87    // @todo remove me after debugging with legion done
88    Tick instCount() { return instCnt; }
89
90    /** The next cycle the CPU should be scheduled, given a cache
91     * access or quiesce event returning on this cycle.  This function
92     * may return curTick if the CPU should run on the current cycle.
93     */
94    Tick nextCycle();
95
96    /** The next cycle the CPU should be scheduled, given a cache
97     * access or quiesce event returning on the given Tick.  This
98     * function may return curTick if the CPU should run on the
99     * current cycle.
100     * @param begin_tick The tick that the event is completing on.
101     */
102    Tick nextCycle(Tick begin_tick);
103
104#if FULL_SYSTEM
105  protected:
106//    uint64_t interrupts[TheISA::NumInterruptLevels];
107//    uint64_t intstatus;
108    TheISA::Interrupts interrupts;
109
110  public:
111    virtual void post_interrupt(int int_num, int index);
112    virtual void clear_interrupt(int int_num, int index);
113    virtual void clear_interrupts();
114    virtual uint64_t get_interrupts(int int_num);
115
116    bool check_interrupts(ThreadContext * tc) const
117    { return interrupts.check_interrupts(tc); }
118
119    class ProfileEvent : public Event
120    {
121      private:
122        BaseCPU *cpu;
123        int interval;
124
125      public:
126        ProfileEvent(BaseCPU *cpu, int interval);
127        void process();
128    };
129    ProfileEvent *profileEvent;
130#endif
131
132  protected:
133    std::vector<ThreadContext *> threadContexts;
134    std::vector<TheISA::Predecoder *> predecoders;
135
136    Trace::InstTracer * tracer;
137
138  public:
139
140    /// Provide access to the tracer pointer
141    Trace::InstTracer * getTracer() { return tracer; }
142
143    /// Notify the CPU that the indicated context is now active.  The
144    /// delay parameter indicates the number of ticks to wait before
145    /// executing (typically 0 or 1).
146    virtual void activateContext(int thread_num, int delay) {}
147
148    /// Notify the CPU that the indicated context is now suspended.
149    virtual void suspendContext(int thread_num) {}
150
151    /// Notify the CPU that the indicated context is now deallocated.
152    virtual void deallocateContext(int thread_num) {}
153
154    /// Notify the CPU that the indicated context is now halted.
155    virtual void haltContext(int thread_num) {}
156
157   /// Given a Thread Context pointer return the thread num
158   int findContext(ThreadContext *tc);
159
160   /// Given a thread num get tho thread context for it
161   ThreadContext *getContext(int tn) { return threadContexts[tn]; }
162
163  public:
164    struct Params
165    {
166        std::string name;
167        int numberOfThreads;
168        bool deferRegistration;
169        Counter max_insts_any_thread;
170        Counter max_insts_all_threads;
171        Counter max_loads_any_thread;
172        Counter max_loads_all_threads;
173        Tick clock;
174        bool functionTrace;
175        Tick functionTraceStart;
176        System *system;
177        int cpu_id;
178        Trace::InstTracer * tracer;
179
180        Tick phase;
181#if FULL_SYSTEM
182        Tick profile;
183
184        bool do_statistics_insts;
185        bool do_checkpoint_insts;
186        bool do_quiesce;
187#endif
188        Tick progress_interval;
189        BaseCPU *checker;
190
191        Params();
192    };
193
194    const Params *params;
195
196    BaseCPU(Params *params);
197    virtual ~BaseCPU();
198
199    virtual void init();
200    virtual void startup();
201    virtual void regStats();
202
203    virtual void activateWhenReady(int tid) {};
204
205    void registerThreadContexts();
206
207    /// Prepare for another CPU to take over execution.  When it is
208    /// is ready (drained pipe) it signals the sampler.
209    virtual void switchOut();
210
211    /// Take over execution from the given CPU.  Used for warm-up and
212    /// sampling.
213    virtual void takeOverFrom(BaseCPU *, Port *ic, Port *dc);
214
215    /**
216     *  Number of threads we're actually simulating (<= SMT_MAX_THREADS).
217     * This is a constant for the duration of the simulation.
218     */
219    int number_of_threads;
220
221    /**
222     * Vector of per-thread instruction-based event queues.  Used for
223     * scheduling events based on number of instructions committed by
224     * a particular thread.
225     */
226    EventQueue **comInstEventQueue;
227
228    /**
229     * Vector of per-thread load-based event queues.  Used for
230     * scheduling events based on number of loads committed by
231     *a particular thread.
232     */
233    EventQueue **comLoadEventQueue;
234
235    System *system;
236
237    Tick phase;
238
239#if FULL_SYSTEM
240    /**
241     * Serialize this object to the given output stream.
242     * @param os The stream to serialize to.
243     */
244    virtual void serialize(std::ostream &os);
245
246    /**
247     * Reconstruct the state of this object from a checkpoint.
248     * @param cp The checkpoint use.
249     * @param section The section name of this object
250     */
251    virtual void unserialize(Checkpoint *cp, const std::string &section);
252
253#endif
254
255    /**
256     * Return pointer to CPU's branch predictor (NULL if none).
257     * @return Branch predictor pointer.
258     */
259    virtual BranchPred *getBranchPred() { return NULL; };
260
261    virtual Counter totalInstructions() const { return 0; }
262
263    // Function tracing
264  private:
265    bool functionTracingEnabled;
266    std::ostream *functionTraceStream;
267    Addr currentFunctionStart;
268    Addr currentFunctionEnd;
269    Tick functionEntryTick;
270    void enableFunctionTrace();
271    void traceFunctionsInternal(Addr pc);
272
273  protected:
274    void traceFunctions(Addr pc)
275    {
276        if (functionTracingEnabled)
277            traceFunctionsInternal(pc);
278    }
279
280  private:
281    static std::vector<BaseCPU *> cpuList;   //!< Static global cpu list
282
283  public:
284    static int numSimulatedCPUs() { return cpuList.size(); }
285    static Counter numSimulatedInstructions()
286    {
287        Counter total = 0;
288
289        int size = cpuList.size();
290        for (int i = 0; i < size; ++i)
291            total += cpuList[i]->totalInstructions();
292
293        return total;
294    }
295
296  public:
297    // Number of CPU cycles simulated
298    Stats::Scalar<> numCycles;
299};
300
301#endif // __CPU_BASE_HH__
302