base.hh revision 2103
12SN/A/* 22188SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A */ 282665SN/A 292665SN/A#ifndef __CPU_BASE_HH__ 302665SN/A#define __CPU_BASE_HH__ 312665SN/A 322SN/A#include <vector> 332SN/A 342SN/A#include "base/statistics.hh" 352SN/A#include "config/full_system.hh" 362465SN/A#include "cpu/sampler/sampler.hh" 371717SN/A#include "sim/eventq.hh" 382683Sktlim@umich.edu#include "sim/sim_object.hh" 392680SN/A#include "targetarch/isa_traits.hh" 402SN/A 411858SN/A#if FULL_SYSTEM 423565Sgblack@eecs.umich.educlass System; 431917SN/A#endif 441070SN/A 451917SN/Aclass BranchPred; 462188SN/Aclass ExecContext; 471917SN/A 482290SN/Aclass BaseCPU : public SimObject 491070SN/A{ 501917SN/A protected: 512170SN/A // CPU's clock period in terms of the number of ticks of curTime. 522SN/A Tick clock; 53360SN/A 542519SN/A public: 552420SN/A inline Tick frequency() const { return Clock::Frequency / clock; } 562SN/A inline Tick cycles(int numCycles) const { return clock * numCycles; } 572SN/A inline Tick curCycle() const { return curTick / clock; } 582SN/A 592SN/A#if FULL_SYSTEM 602SN/A protected: 611858SN/A uint64_t interrupts[NumInterruptLevels]; 622683Sktlim@umich.edu uint64_t intstatus; 633453Sgblack@eecs.umich.edu 642683Sktlim@umich.edu public: 653402Sktlim@umich.edu virtual void post_interrupt(int int_num, int index); 662683Sktlim@umich.edu virtual void clear_interrupt(int int_num, int index); 672521SN/A virtual void clear_interrupts(); 682SN/A bool checkInterrupts; 692683Sktlim@umich.edu 702190SN/A bool check_interrupt(int int_num) const { 712680SN/A if (int_num > NumInterruptLevels) 722290SN/A panic("int_num out of bounds\n"); 732526SN/A 741917SN/A return interrupts[int_num] != 0; 751917SN/A } 761982SN/A 771917SN/A bool check_interrupts() const { return intstatus != 0; } 782683Sktlim@umich.edu uint64_t intr_status() const { return intstatus; } 792683Sktlim@umich.edu 801917SN/A class ProfileEvent : public Event 811917SN/A { 821917SN/A private: 831917SN/A BaseCPU *cpu; 841917SN/A int interval; 851917SN/A 861917SN/A public: 871917SN/A ProfileEvent(BaseCPU *cpu, int interval); 882521SN/A void process(); 892341SN/A }; 903548Sgblack@eecs.umich.edu ProfileEvent *profileEvent; 912341SN/A#endif 922341SN/A 932341SN/A protected: 942SN/A std::vector<ExecContext *> execContexts; 952SN/A 962683Sktlim@umich.edu public: 973402Sktlim@umich.edu 983402Sktlim@umich.edu /// Notify the CPU that the indicated context is now active. The 992683Sktlim@umich.edu /// delay parameter indicates the number of ticks to wait before 1002SN/A /// executing (typically 0 or 1). 1012526SN/A virtual void activateContext(int thread_num, int delay) {} 1022683Sktlim@umich.edu 1032SN/A /// Notify the CPU that the indicated context is now suspended. 1042190SN/A virtual void suspendContext(int thread_num) {} 1052862Sktlim@umich.edu 1062862Sktlim@umich.edu /// Notify the CPU that the indicated context is now deallocated. 1072864Sktlim@umich.edu virtual void deallocateContext(int thread_num) {} 1082862Sktlim@umich.edu 1093402Sktlim@umich.edu /// Notify the CPU that the indicated context is now halted. 1102862Sktlim@umich.edu virtual void haltContext(int thread_num) {} 1113402Sktlim@umich.edu 1122862Sktlim@umich.edu public: 1132190SN/A struct Params 1142683Sktlim@umich.edu { 1152862Sktlim@umich.edu std::string name; 1162190SN/A int numberOfThreads; 1172190SN/A bool deferRegistration; 1182683Sktlim@umich.edu Counter max_insts_any_thread; 1191070SN/A Counter max_insts_all_threads; 1203486Sktlim@umich.edu Counter max_loads_any_thread; 1213486Sktlim@umich.edu Counter max_loads_all_threads; 1223486Sktlim@umich.edu Tick clock; 1233486Sktlim@umich.edu bool functionTrace; 1242680SN/A Tick functionTraceStart; 1251070SN/A#if FULL_SYSTEM 1261070SN/A System *system; 1271917SN/A int cpu_id; 1282683Sktlim@umich.edu Tick profile; 129180SN/A#endif 130180SN/A 1311858SN/A Params(); 1322235SN/A }; 133180SN/A 1342235SN/A const Params *params; 135180SN/A 136180SN/A BaseCPU(Params *params); 1372862Sktlim@umich.edu virtual ~BaseCPU(); 1382862Sktlim@umich.edu 1392313SN/A virtual void init(); 1402313SN/A virtual void startup(); 1412680SN/A virtual void regStats(); 1422313SN/A 1432680SN/A virtual void activateWhenReady(int tid) {}; 1442313SN/A 1452313SN/A void registerExecContexts(); 1462680SN/A 1472313SN/A /// Prepare for another CPU to take over execution. When it is 1482361SN/A /// is ready (drained pipe) it signals the sampler. 1493548Sgblack@eecs.umich.edu virtual void switchOut(Sampler *); 1502361SN/A 1512361SN/A /// Take over execution from the given CPU. Used for warm-up and 1522361SN/A /// sampling. 1532235SN/A virtual void takeOverFrom(BaseCPU *); 154180SN/A 155180SN/A /** 156180SN/A * Number of threads we're actually simulating (<= SMT_MAX_THREADS). 1572680SN/A * This is a constant for the duration of the simulation. 158180SN/A */ 159180SN/A int number_of_threads; 1602SN/A 1612864Sktlim@umich.edu /** 1622864Sktlim@umich.edu * Vector of per-thread instruction-based event queues. Used for 1632864Sktlim@umich.edu * scheduling events based on number of instructions committed by 1642864Sktlim@umich.edu * a particular thread. 1652864Sktlim@umich.edu */ 1662864Sktlim@umich.edu EventQueue **comInstEventQueue; 1672864Sktlim@umich.edu 1682864Sktlim@umich.edu /** 1692864Sktlim@umich.edu * Vector of per-thread load-based event queues. Used for 1703548Sgblack@eecs.umich.edu * scheduling events based on number of loads committed by 1712864Sktlim@umich.edu *a particular thread. 1722864Sktlim@umich.edu */ 1732864Sktlim@umich.edu EventQueue **comLoadEventQueue; 1742864Sktlim@umich.edu 1752864Sktlim@umich.edu#if FULL_SYSTEM 1762864Sktlim@umich.edu System *system; 1772864Sktlim@umich.edu 1782862Sktlim@umich.edu /** 1792862Sktlim@umich.edu * Serialize this object to the given output stream. 1802862Sktlim@umich.edu * @param os The stream to serialize to. 1812862Sktlim@umich.edu */ 1822862Sktlim@umich.edu virtual void serialize(std::ostream &os); 1832862Sktlim@umich.edu 1842862Sktlim@umich.edu /** 1852862Sktlim@umich.edu * Reconstruct the state of this object from a checkpoint. 1862862Sktlim@umich.edu * @param cp The checkpoint use. 1872915Sktlim@umich.edu * @param section The section name of this object 1882862Sktlim@umich.edu */ 1892862Sktlim@umich.edu virtual void unserialize(Checkpoint *cp, const std::string §ion); 1902862Sktlim@umich.edu 1912683Sktlim@umich.edu#endif 192217SN/A 1932862Sktlim@umich.edu /** 194223SN/A * Return pointer to CPU's branch predictor (NULL if none). 195223SN/A * @return Branch predictor pointer. 196217SN/A */ 197217SN/A virtual BranchPred *getBranchPred() { return NULL; }; 198217SN/A 199217SN/A virtual Counter totalInstructions() const { return 0; } 2002683Sktlim@umich.edu 201217SN/A // Function tracing 2022862Sktlim@umich.edu private: 203237SN/A bool functionTracingEnabled; 204223SN/A std::ostream *functionTraceStream; 205217SN/A Addr currentFunctionStart; 206217SN/A Addr currentFunctionEnd; 2072683Sktlim@umich.edu Tick functionEntryTick; 2082683Sktlim@umich.edu void enableFunctionTrace(); 2092683Sktlim@umich.edu void traceFunctionsInternal(Addr pc); 2102683Sktlim@umich.edu 2112683Sktlim@umich.edu protected: 2122683Sktlim@umich.edu void traceFunctions(Addr pc) 2132683Sktlim@umich.edu { 2142683Sktlim@umich.edu if (functionTracingEnabled) 215217SN/A traceFunctionsInternal(pc); 216217SN/A } 2172683Sktlim@umich.edu 2182SN/A private: 2192680SN/A static std::vector<BaseCPU *> cpuList; //!< Static global cpu list 2202SN/A 2212SN/A public: 2222188SN/A static int numSimulatedCPUs() { return cpuList.size(); } 2232188SN/A static Counter numSimulatedInstructions() 2242680SN/A { 2252683Sktlim@umich.edu Counter total = 0; 2262290SN/A 2272290SN/A int size = cpuList.size(); 2282290SN/A for (int i = 0; i < size; ++i) 2292680SN/A total += cpuList[i]->totalInstructions(); 2302290SN/A 2312290SN/A return total; 2322683Sktlim@umich.edu } 233393SN/A 234393SN/A public: 235393SN/A // Number of CPU cycles simulated 2362683Sktlim@umich.edu Stats::Scalar<> numCycles; 237393SN/A}; 2382680SN/A 239393SN/A#endif // __CPU_BASE_HH__ 240393SN/A