base.hh revision 1492
12SN/A/*
21762SN/A * Copyright (c) 2002-2004 The Regents of The University of Michigan
32SN/A * All rights reserved.
42SN/A *
52SN/A * Redistribution and use in source and binary forms, with or without
62SN/A * modification, are permitted provided that the following conditions are
72SN/A * met: redistributions of source code must retain the above copyright
82SN/A * notice, this list of conditions and the following disclaimer;
92SN/A * redistributions in binary form must reproduce the above copyright
102SN/A * notice, this list of conditions and the following disclaimer in the
112SN/A * documentation and/or other materials provided with the distribution;
122SN/A * neither the name of the copyright holders nor the names of its
132SN/A * contributors may be used to endorse or promote products derived from
142SN/A * this software without specific prior written permission.
152SN/A *
162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665Ssaidi@eecs.umich.edu */
282665Ssaidi@eecs.umich.edu
292665Ssaidi@eecs.umich.edu#ifndef __BASE_CPU_HH__
302665Ssaidi@eecs.umich.edu#define __BASE_CPU_HH__
312665Ssaidi@eecs.umich.edu
322SN/A#include <vector>
332SN/A
342SN/A#include "base/statistics.hh"
352SN/A#include "cpu/sampling_cpu/sampling_cpu.hh"
362SN/A#include "sim/eventq.hh"
372973Sgblack@eecs.umich.edu#include "sim/sim_object.hh"
3856SN/A#include "targetarch/isa_traits.hh"
391717SN/A
402518SN/A#ifdef FULL_SYSTEM
4156SN/Aclass System;
422518SN/A#endif
432518SN/A
442SN/Aclass BranchPred;
453065Sgblack@eecs.umich.educlass ExecContext;
463065Sgblack@eecs.umich.edu
473065Sgblack@eecs.umich.educlass BaseCPU : public SimObject
482SN/A{
492973Sgblack@eecs.umich.edu#ifdef FULL_SYSTEM
502SN/A  protected:
512SN/A    Tick frequency;
522SN/A    uint64_t interrupts[NumInterruptLevels];
532SN/A    uint64_t intstatus;
542SN/A
552SN/A  public:
562SN/A    virtual void post_interrupt(int int_num, int index);
572SN/A    virtual void clear_interrupt(int int_num, int index);
582SN/A    virtual void clear_interrupts();
592SN/A    bool checkInterrupts;
602973Sgblack@eecs.umich.edu
612973Sgblack@eecs.umich.edu    bool check_interrupt(int int_num) const {
623065Sgblack@eecs.umich.edu        if (int_num > NumInterruptLevels)
633380Sgblack@eecs.umich.edu            panic("int_num out of bounds\n");
643380Sgblack@eecs.umich.edu
653380Sgblack@eecs.umich.edu        return interrupts[int_num] != 0;
663380Sgblack@eecs.umich.edu    }
673380Sgblack@eecs.umich.edu
683380Sgblack@eecs.umich.edu    bool check_interrupts() const { return intstatus != 0; }
693380Sgblack@eecs.umich.edu    uint64_t intr_status() const { return intstatus; }
703380Sgblack@eecs.umich.edu
713380Sgblack@eecs.umich.edu    Tick getFreq() const { return frequency; }
723380Sgblack@eecs.umich.edu#endif
733380Sgblack@eecs.umich.edu
743380Sgblack@eecs.umich.edu  protected:
753380Sgblack@eecs.umich.edu    std::vector<ExecContext *> execContexts;
763380Sgblack@eecs.umich.edu
773065Sgblack@eecs.umich.edu  public:
783380Sgblack@eecs.umich.edu
793380Sgblack@eecs.umich.edu    /// Notify the CPU that the indicated context is now active.  The
803059Sgblack@eecs.umich.edu    /// delay parameter indicates the number of ticks to wait before
813380Sgblack@eecs.umich.edu    /// executing (typically 0 or 1).
823059Sgblack@eecs.umich.edu    virtual void activateContext(int thread_num, int delay) {}
833380Sgblack@eecs.umich.edu
843380Sgblack@eecs.umich.edu    /// Notify the CPU that the indicated context is now suspended.
853059Sgblack@eecs.umich.edu    virtual void suspendContext(int thread_num) {}
863380Sgblack@eecs.umich.edu
873380Sgblack@eecs.umich.edu    /// Notify the CPU that the indicated context is now deallocated.
883380Sgblack@eecs.umich.edu    virtual void deallocateContext(int thread_num) {}
893380Sgblack@eecs.umich.edu
903380Sgblack@eecs.umich.edu    /// Notify the CPU that the indicated context is now halted.
913380Sgblack@eecs.umich.edu    virtual void haltContext(int thread_num) {}
923380Sgblack@eecs.umich.edu
933380Sgblack@eecs.umich.edu  public:
943380Sgblack@eecs.umich.edu
953380Sgblack@eecs.umich.edu#ifdef FULL_SYSTEM
963380Sgblack@eecs.umich.edu    BaseCPU(const std::string &_name, int _number_of_threads, bool _def_reg,
973380Sgblack@eecs.umich.edu            Counter max_insts_any_thread, Counter max_insts_all_threads,
983380Sgblack@eecs.umich.edu            Counter max_loads_any_thread, Counter max_loads_all_threads,
993380Sgblack@eecs.umich.edu            System *_system, Tick freq,
1003059Sgblack@eecs.umich.edu            bool _function_trace = false, Tick _function_trace_start = 0);
1013380Sgblack@eecs.umich.edu#else
1023380Sgblack@eecs.umich.edu    BaseCPU(const std::string &_name, int _number_of_threads, bool _def_reg,
1033380Sgblack@eecs.umich.edu            Counter max_insts_any_thread = 0,
1043380Sgblack@eecs.umich.edu            Counter max_insts_all_threads = 0,
1053380Sgblack@eecs.umich.edu            Counter max_loads_any_thread = 0,
1063380Sgblack@eecs.umich.edu            Counter max_loads_all_threads = 0,
1073380Sgblack@eecs.umich.edu            bool _function_trace = false, Tick _function_trace_start = 0);
1083380Sgblack@eecs.umich.edu#endif
1093059Sgblack@eecs.umich.edu
1103059Sgblack@eecs.umich.edu    virtual ~BaseCPU();
1113380Sgblack@eecs.umich.edu
1123380Sgblack@eecs.umich.edu    virtual void init();
1133380Sgblack@eecs.umich.edu    virtual void regStats();
1143380Sgblack@eecs.umich.edu
1153380Sgblack@eecs.umich.edu    bool deferRegistration;
1163380Sgblack@eecs.umich.edu    void registerExecContexts();
1173380Sgblack@eecs.umich.edu
1183380Sgblack@eecs.umich.edu    /// Prepare for another CPU to take over execution.  When it is
1193380Sgblack@eecs.umich.edu    /// is ready (drained pipe) it signals the sampler.
1203380Sgblack@eecs.umich.edu    virtual void switchOut(SamplingCPU *);
1213380Sgblack@eecs.umich.edu
1223059Sgblack@eecs.umich.edu    /// Take over execution from the given CPU.  Used for warm-up and
1233065Sgblack@eecs.umich.edu    /// sampling.
1242973Sgblack@eecs.umich.edu    virtual void takeOverFrom(BaseCPU *);
1252973Sgblack@eecs.umich.edu
1261968SN/A    /**
1273064Sgblack@eecs.umich.edu     *  Number of threads we're actually simulating (<= SMT_MAX_THREADS).
1281968SN/A     * This is a constant for the duration of the simulation.
1291968SN/A     */
1301968SN/A    int number_of_threads;
1311968SN/A
1321967SN/A    /**
1331967SN/A     * Vector of per-thread instruction-based event queues.  Used for
1341967SN/A     * scheduling events based on number of instructions committed by
1351967SN/A     * a particular thread.
1361967SN/A     */
1371967SN/A    EventQueue **comInstEventQueue;
1381967SN/A
1391967SN/A    /**
1401967SN/A     * Vector of per-thread load-based event queues.  Used for
1411967SN/A     * scheduling events based on number of loads committed by
1421904SN/A     *a particular thread.
1431904SN/A     */
1441904SN/A    EventQueue **comLoadEventQueue;
1451904SN/A
146452SN/A#ifdef FULL_SYSTEM
1473064Sgblack@eecs.umich.edu    System *system;
1482SN/A
1491904SN/A    /**
1501904SN/A     * Serialize this object to the given output stream.
1512SN/A     * @param os The stream to serialize to.
1521904SN/A     */
1533064Sgblack@eecs.umich.edu    virtual void serialize(std::ostream &os);
1542SN/A
1552SN/A    /**
1561904SN/A     * Reconstruct the state of this object from a checkpoint.
1571904SN/A     * @param cp The checkpoint use.
1581904SN/A     * @param section The section name of this object
1592299SN/A     */
1602299SN/A    virtual void unserialize(Checkpoint *cp, const std::string &section);
1611904SN/A
1621904SN/A#endif
1631904SN/A
1641904SN/A    /**
1651904SN/A     * Return pointer to CPU's branch predictor (NULL if none).
1661904SN/A     * @return Branch predictor pointer.
1671904SN/A     */
168452SN/A    virtual BranchPred *getBranchPred() { return NULL; };
1691904SN/A
1701904SN/A    virtual Counter totalInstructions() const { return 0; }
1711904SN/A
1722SN/A    // Function tracing
1732SN/A  private:
1741904SN/A    bool functionTracingEnabled;
1751904SN/A    std::ostream *functionTraceStream;
1761904SN/A    Addr currentFunctionStart;
1771904SN/A    Addr currentFunctionEnd;
1781904SN/A    Tick functionEntryTick;
1791904SN/A    void enableFunctionTrace();
1802SN/A    void traceFunctionsInternal(Addr pc);
1811904SN/A
1822SN/A  protected:
1832SN/A    void traceFunctions(Addr pc)
1841904SN/A    {
1852SN/A        if (functionTracingEnabled)
1861904SN/A            traceFunctionsInternal(pc);
1871904SN/A    }
1881904SN/A
1891904SN/A  private:
1901904SN/A    static std::vector<BaseCPU *> cpuList;   //!< Static global cpu list
1911904SN/A
1921904SN/A  public:
1931904SN/A    static int numSimulatedCPUs() { return cpuList.size(); }
1941904SN/A    static Counter numSimulatedInstructions()
1951904SN/A    {
1961904SN/A        Counter total = 0;
1971904SN/A
1981904SN/A        int size = cpuList.size();
1991904SN/A        for (int i = 0; i < size; ++i)
2001904SN/A            total += cpuList[i]->totalInstructions();
2011904SN/A
2021904SN/A        return total;
2031904SN/A    }
2041904SN/A
2051904SN/A  public:
2062525SN/A    // Number of CPU cycles simulated
2071904SN/A    Stats::Scalar<> numCycles;
2082525SN/A};
2092525SN/A
2102525SN/A#endif // __BASE_CPU_HH__
2111904SN/A