base.hh revision 1492 
1/*
2 * Copyright (c) 2002-2004 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __BASE_CPU_HH__
30#define __BASE_CPU_HH__
31
32#include <vector>
33
34#include "base/statistics.hh"
35#include "cpu/sampling_cpu/sampling_cpu.hh"
36#include "sim/eventq.hh"
37#include "sim/sim_object.hh"
38#include "targetarch/isa_traits.hh"
39
40#ifdef FULL_SYSTEM
41class System;
42#endif
43
44class BranchPred;
45class ExecContext;
46
47class BaseCPU : public SimObject
48{
49#ifdef FULL_SYSTEM
50  protected:
51    Tick frequency;
52    uint64_t interrupts[NumInterruptLevels];
53    uint64_t intstatus;
54
55  public:
56    virtual void post_interrupt(int int_num, int index);
57    virtual void clear_interrupt(int int_num, int index);
58    virtual void clear_interrupts();
59    bool checkInterrupts;
60
61    bool check_interrupt(int int_num) const {
62        if (int_num > NumInterruptLevels)
63            panic("int_num out of bounds\n");
64
65        return interrupts[int_num] != 0;
66    }
67
68    bool check_interrupts() const { return intstatus != 0; }
69    uint64_t intr_status() const { return intstatus; }
70
71    Tick getFreq() const { return frequency; }
72#endif
73
74  protected:
75    std::vector<ExecContext *> execContexts;
76
77  public:
78
79    /// Notify the CPU that the indicated context is now active.  The
80    /// delay parameter indicates the number of ticks to wait before
81    /// executing (typically 0 or 1).
82    virtual void activateContext(int thread_num, int delay) {}
83
84    /// Notify the CPU that the indicated context is now suspended.
85    virtual void suspendContext(int thread_num) {}
86
87    /// Notify the CPU that the indicated context is now deallocated.
88    virtual void deallocateContext(int thread_num) {}
89
90    /// Notify the CPU that the indicated context is now halted.
91    virtual void haltContext(int thread_num) {}
92
93  public:
94
95#ifdef FULL_SYSTEM
96    BaseCPU(const std::string &_name, int _number_of_threads, bool _def_reg,
97            Counter max_insts_any_thread, Counter max_insts_all_threads,
98            Counter max_loads_any_thread, Counter max_loads_all_threads,
99            System *_system, Tick freq,
100            bool _function_trace = false, Tick _function_trace_start = 0);
101#else
102    BaseCPU(const std::string &_name, int _number_of_threads, bool _def_reg,
103            Counter max_insts_any_thread = 0,
104            Counter max_insts_all_threads = 0,
105            Counter max_loads_any_thread = 0,
106            Counter max_loads_all_threads = 0,
107            bool _function_trace = false, Tick _function_trace_start = 0);
108#endif
109
110    virtual ~BaseCPU();
111
112    virtual void init();
113    virtual void regStats();
114
115    bool deferRegistration;
116    void registerExecContexts();
117
118    /// Prepare for another CPU to take over execution.  When it is
119    /// is ready (drained pipe) it signals the sampler.
120    virtual void switchOut(SamplingCPU *);
121
122    /// Take over execution from the given CPU.  Used for warm-up and
123    /// sampling.
124    virtual void takeOverFrom(BaseCPU *);
125
126    /**
127     *  Number of threads we're actually simulating (<= SMT_MAX_THREADS).
128     * This is a constant for the duration of the simulation.
129     */
130    int number_of_threads;
131
132    /**
133     * Vector of per-thread instruction-based event queues.  Used for
134     * scheduling events based on number of instructions committed by
135     * a particular thread.
136     */
137    EventQueue **comInstEventQueue;
138
139    /**
140     * Vector of per-thread load-based event queues.  Used for
141     * scheduling events based on number of loads committed by
142     *a particular thread.
143     */
144    EventQueue **comLoadEventQueue;
145
146#ifdef FULL_SYSTEM
147    System *system;
148
149    /**
150     * Serialize this object to the given output stream.
151     * @param os The stream to serialize to.
152     */
153    virtual void serialize(std::ostream &os);
154
155    /**
156     * Reconstruct the state of this object from a checkpoint.
157     * @param cp The checkpoint use.
158     * @param section The section name of this object
159     */
160    virtual void unserialize(Checkpoint *cp, const std::string &section);
161
162#endif
163
164    /**
165     * Return pointer to CPU's branch predictor (NULL if none).
166     * @return Branch predictor pointer.
167     */
168    virtual BranchPred *getBranchPred() { return NULL; };
169
170    virtual Counter totalInstructions() const { return 0; }
171
172    // Function tracing
173  private:
174    bool functionTracingEnabled;
175    std::ostream *functionTraceStream;
176    Addr currentFunctionStart;
177    Addr currentFunctionEnd;
178    Tick functionEntryTick;
179    void enableFunctionTrace();
180    void traceFunctionsInternal(Addr pc);
181
182  protected:
183    void traceFunctions(Addr pc)
184    {
185        if (functionTracingEnabled)
186            traceFunctionsInternal(pc);
187    }
188
189  private:
190    static std::vector<BaseCPU *> cpuList;   //!< Static global cpu list
191
192  public:
193    static int numSimulatedCPUs() { return cpuList.size(); }
194    static Counter numSimulatedInstructions()
195    {
196        Counter total = 0;
197
198        int size = cpuList.size();
199        for (int i = 0; i < size; ++i)
200            total += cpuList[i]->totalInstructions();
201
202        return total;
203    }
204
205  public:
206    // Number of CPU cycles simulated
207    Stats::Scalar<> numCycles;
208};
209
210#endif // __BASE_CPU_HH__
211