base.hh revision 1129
13006SN/A/* 23006SN/A * Copyright (c) 2002-2004 The Regents of The University of Michigan 34398SN/A * All rights reserved. 410488Snilay@cs.wisc.edu * 510488Snilay@cs.wisc.edu * Redistribution and use in source and binary forms, with or without 68540SN/A * modification, are permitted provided that the following conditions are 711268Satgutier@umich.edu * met: redistributions of source code must retain the above copyright 811268Satgutier@umich.edu * notice, this list of conditions and the following disclaimer; 911268Satgutier@umich.edu * redistributions in binary form must reproduce the above copyright 1011268Satgutier@umich.edu * notice, this list of conditions and the following disclaimer in the 1111268Satgutier@umich.edu * documentation and/or other materials provided with the distribution; 1210488Snilay@cs.wisc.edu * neither the name of the copyright holders nor the names of its 1310488Snilay@cs.wisc.edu * contributors may be used to endorse or promote products derived from 1410036SAli.Saidi@ARM.com * this software without specific prior written permission. 1510036SAli.Saidi@ARM.com * 1610488Snilay@cs.wisc.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1710488Snilay@cs.wisc.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1810488Snilay@cs.wisc.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1910488Snilay@cs.wisc.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2010488Snilay@cs.wisc.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2110488Snilay@cs.wisc.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2210488Snilay@cs.wisc.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2310488Snilay@cs.wisc.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2410488Snilay@cs.wisc.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2510488Snilay@cs.wisc.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2610488Snilay@cs.wisc.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2710488Snilay@cs.wisc.edu */ 2810488Snilay@cs.wisc.edu 2910488Snilay@cs.wisc.edu#ifndef __BASE_CPU_HH__ 3010488Snilay@cs.wisc.edu#define __BASE_CPU_HH__ 3110488Snilay@cs.wisc.edu 3210488Snilay@cs.wisc.edu#include <vector> 3310488Snilay@cs.wisc.edu 3410488Snilay@cs.wisc.edu#include "base/statistics.hh" 3510488Snilay@cs.wisc.edu#include "sim/eventq.hh" 3610488Snilay@cs.wisc.edu#include "sim/sim_object.hh" 3710488Snilay@cs.wisc.edu#include "targetarch/isa_traits.hh" 3810036SAli.Saidi@ARM.com 398540SN/A#ifdef FULL_SYSTEM 408540SN/Aclass System; 418540SN/A#endif 428540SN/A 438540SN/Aclass BranchPred; 448540SN/Aclass ExecContext; 455510SN/A 465510SN/Aclass BaseCPU : public SimObject 478540SN/A{ 488540SN/A#ifdef FULL_SYSTEM 498540SN/A protected: 508540SN/A Tick frequency; 518540SN/A uint64_t interrupts[NumInterruptLevels]; 528540SN/A uint64_t intstatus; 538540SN/A 545510SN/A public: 555510SN/A virtual void post_interrupt(int int_num, int index); 568540SN/A virtual void clear_interrupt(int int_num, int index); 5710488Snilay@cs.wisc.edu virtual void clear_interrupts(); 5810488Snilay@cs.wisc.edu 598540SN/A bool check_interrupt(int int_num) const { 607935SN/A if (int_num > NumInterruptLevels) 6110488Snilay@cs.wisc.edu panic("int_num out of bounds\n"); 6210488Snilay@cs.wisc.edu 6310488Snilay@cs.wisc.edu return interrupts[int_num] != 0; 648540SN/A } 6510488Snilay@cs.wisc.edu 6610488Snilay@cs.wisc.edu bool check_interrupts() const { return intstatus != 0; } 6710488Snilay@cs.wisc.edu uint64_t intr_status() const { return intstatus; } 687935SN/A 6910488Snilay@cs.wisc.edu Tick getFreq() const { return frequency; } 7010488Snilay@cs.wisc.edu#endif 717935SN/A 727935SN/A protected: 7310488Snilay@cs.wisc.edu std::vector<ExecContext *> execContexts; 7410488Snilay@cs.wisc.edu 7510488Snilay@cs.wisc.edu public: 767935SN/A 7710488Snilay@cs.wisc.edu /// Notify the CPU that the indicated context is now active. The 788540SN/A /// delay parameter indicates the number of ticks to wait before 798540SN/A /// executing (typically 0 or 1). 8010488Snilay@cs.wisc.edu virtual void activateContext(int thread_num, int delay) {} 8110488Snilay@cs.wisc.edu 8210488Snilay@cs.wisc.edu /// Notify the CPU that the indicated context is now suspended. 8310488Snilay@cs.wisc.edu virtual void suspendContext(int thread_num) {} 8410488Snilay@cs.wisc.edu 8510488Snilay@cs.wisc.edu /// Notify the CPU that the indicated context is now deallocated. 8610488Snilay@cs.wisc.edu virtual void deallocateContext(int thread_num) {} 8710488Snilay@cs.wisc.edu 8810488Snilay@cs.wisc.edu /// Notify the CPU that the indicated context is now halted. 8910488Snilay@cs.wisc.edu virtual void haltContext(int thread_num) {} 9010488Snilay@cs.wisc.edu 9110488Snilay@cs.wisc.edu public: 9210488Snilay@cs.wisc.edu 9310488Snilay@cs.wisc.edu#ifdef FULL_SYSTEM 9410488Snilay@cs.wisc.edu BaseCPU(const std::string &_name, int _number_of_threads, bool _def_reg, 9510488Snilay@cs.wisc.edu Counter max_insts_any_thread, Counter max_insts_all_threads, 9610488Snilay@cs.wisc.edu Counter max_loads_any_thread, Counter max_loads_all_threads, 9710488Snilay@cs.wisc.edu System *_system, Tick freq); 9810488Snilay@cs.wisc.edu#else 9910488Snilay@cs.wisc.edu BaseCPU(const std::string &_name, int _number_of_threads, bool _def_reg, 10010488Snilay@cs.wisc.edu Counter max_insts_any_thread = 0, 10110488Snilay@cs.wisc.edu Counter max_insts_all_threads = 0, 10210488Snilay@cs.wisc.edu Counter max_loads_any_thread = 0, 10310488Snilay@cs.wisc.edu Counter max_loads_all_threads = 0); 10410488Snilay@cs.wisc.edu#endif 10510488Snilay@cs.wisc.edu 10610488Snilay@cs.wisc.edu virtual ~BaseCPU() {} 10710488Snilay@cs.wisc.edu 10810488Snilay@cs.wisc.edu virtual void init(); 10910488Snilay@cs.wisc.edu virtual void regStats(); 11010488Snilay@cs.wisc.edu 11110488Snilay@cs.wisc.edu bool deferRegistration; 11210488Snilay@cs.wisc.edu void registerExecContexts(); 11310220Sandreas.hansson@arm.com 11410220Sandreas.hansson@arm.com /// Prepare for another CPU to take over execution. Called by 11510488Snilay@cs.wisc.edu /// takeOverFrom() on its argument. 11611268Satgutier@umich.edu virtual void switchOut(); 11711268Satgutier@umich.edu 11811268Satgutier@umich.edu /// Take over execution from the given CPU. Used for warm-up and 11911268Satgutier@umich.edu /// sampling. 12011268Satgutier@umich.edu virtual void takeOverFrom(BaseCPU *); 12111268Satgutier@umich.edu 12211268Satgutier@umich.edu /** 12311268Satgutier@umich.edu * Number of threads we're actually simulating (<= SMT_MAX_THREADS). 12411268Satgutier@umich.edu * This is a constant for the duration of the simulation. 12511268Satgutier@umich.edu */ 12611268Satgutier@umich.edu int number_of_threads; 12711268Satgutier@umich.edu 12811268Satgutier@umich.edu /** 12911268Satgutier@umich.edu * Vector of per-thread instruction-based event queues. Used for 13011268Satgutier@umich.edu * scheduling events based on number of instructions committed by 13111268Satgutier@umich.edu * a particular thread. 13211268Satgutier@umich.edu */ 13311268Satgutier@umich.edu EventQueue **comInstEventQueue; 13411268Satgutier@umich.edu 13511268Satgutier@umich.edu /** 13611268Satgutier@umich.edu * Vector of per-thread load-based event queues. Used for 1373006SN/A * scheduling events based on number of loads committed by 1383006SN/A *a particular thread. 139 */ 140 EventQueue **comLoadEventQueue; 141 142#ifdef FULL_SYSTEM 143 System *system; 144 145 /** 146 * Serialize this object to the given output stream. 147 * @param os The stream to serialize to. 148 */ 149 virtual void serialize(std::ostream &os); 150 151 /** 152 * Reconstruct the state of this object from a checkpoint. 153 * @param cp The checkpoint use. 154 * @param section The section name of this object 155 */ 156 virtual void unserialize(Checkpoint *cp, const std::string §ion); 157 158#endif 159 160 /** 161 * Return pointer to CPU's branch predictor (NULL if none). 162 * @return Branch predictor pointer. 163 */ 164 virtual BranchPred *getBranchPred() { return NULL; }; 165 166 virtual Counter totalInstructions() const { return 0; } 167 168 private: 169 static std::vector<BaseCPU *> cpuList; //!< Static global cpu list 170 171 public: 172 static int numSimulatedCPUs() { return cpuList.size(); } 173 static Counter numSimulatedInstructions() 174 { 175 Counter total = 0; 176 177 int size = cpuList.size(); 178 for (int i = 0; i < size; ++i) 179 total += cpuList[i]->totalInstructions(); 180 181 return total; 182 } 183 184 public: 185 // Number of CPU cycles simulated 186 Stats::Scalar<> numCycles; 187}; 188 189#endif // __BASE_CPU_HH__ 190