base.hh revision 10464
12SN/A/* 29608Sandreas.hansson@arm.com * Copyright (c) 2011-2013 ARM Limited 38707Sandreas.hansson@arm.com * All rights reserved 48707Sandreas.hansson@arm.com * 58707Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68707Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78707Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88707Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98707Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108707Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118707Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128707Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138707Sandreas.hansson@arm.com * 141762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 157897Shestness@cs.utexas.edu * Copyright (c) 2011 Regents of the University of California 162SN/A * All rights reserved. 172SN/A * 182SN/A * Redistribution and use in source and binary forms, with or without 192SN/A * modification, are permitted provided that the following conditions are 202SN/A * met: redistributions of source code must retain the above copyright 212SN/A * notice, this list of conditions and the following disclaimer; 222SN/A * redistributions in binary form must reproduce the above copyright 232SN/A * notice, this list of conditions and the following disclaimer in the 242SN/A * documentation and/or other materials provided with the distribution; 252SN/A * neither the name of the copyright holders nor the names of its 262SN/A * contributors may be used to endorse or promote products derived from 272SN/A * this software without specific prior written permission. 282SN/A * 292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 422665Ssaidi@eecs.umich.edu * Nathan Binkert 437897Shestness@cs.utexas.edu * Rick Strong 442SN/A */ 452SN/A 461717SN/A#ifndef __CPU_BASE_HH__ 471717SN/A#define __CPU_BASE_HH__ 482SN/A 492SN/A#include <vector> 502SN/A 519850Sandreas.hansson@arm.com// Before we do anything else, check if this build is the NULL ISA, 529850Sandreas.hansson@arm.com// and if so stop here 539850Sandreas.hansson@arm.com#include "config/the_isa.hh" 549850Sandreas.hansson@arm.com#if THE_ISA == NULL_ISA 559850Sandreas.hansson@arm.com#include "arch/null/cpu_dummy.hh" 569850Sandreas.hansson@arm.com#else 578745Sgblack@eecs.umich.edu#include "arch/interrupts.hh" 584182Sgblack@eecs.umich.edu#include "arch/isa_traits.hh" 595664Sgblack@eecs.umich.edu#include "arch/microcode_rom.hh" 60707SN/A#include "base/statistics.hh" 618229Snate@binkert.org#include "mem/mem_object.hh" 6256SN/A#include "sim/eventq.hh" 638779Sgblack@eecs.umich.edu#include "sim/full_system.hh" 644776Sgblack@eecs.umich.edu#include "sim/insttracer.hh" 6510464SAndreas.Sandberg@ARM.com#include "sim/probe/pmu.hh" 669814Sandreas.hansson@arm.com#include "sim/system.hh" 672SN/A 688901Sandreas.hansson@arm.comstruct BaseCPUParams; 692315SN/Aclass CheckerCPU; 702680Sktlim@umich.educlass ThreadContext; 712SN/A 722356SN/Aclass CPUProgressEvent : public Event 732356SN/A{ 742356SN/A protected: 756144Sksewell@umich.edu Tick _interval; 762356SN/A Counter lastNumInst; 772356SN/A BaseCPU *cpu; 786144Sksewell@umich.edu bool _repeatEvent; 792356SN/A 802356SN/A public: 816144Sksewell@umich.edu CPUProgressEvent(BaseCPU *_cpu, Tick ival = 0); 822356SN/A 832356SN/A void process(); 842356SN/A 856144Sksewell@umich.edu void interval(Tick ival) { _interval = ival; } 866144Sksewell@umich.edu Tick interval() { return _interval; } 876144Sksewell@umich.edu 886144Sksewell@umich.edu void repeatEvent(bool repeat) { _repeatEvent = repeat; } 896144Sksewell@umich.edu 905336Shines@cs.fsu.edu virtual const char *description() const; 912356SN/A}; 922356SN/A 932856Srdreslin@umich.educlass BaseCPU : public MemObject 942SN/A{ 951634SN/A protected: 969157Sandreas.hansson@arm.com 973814Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 983814Ssaidi@eecs.umich.edu Tick instCnt; 995712Shsul@eecs.umich.edu // every cpu has an id, put it in the base cpu 1005712Shsul@eecs.umich.edu // Set at initialization, only time a cpuId might change is during a 1015715Shsul@eecs.umich.edu // takeover (which should be done from within the BaseCPU anyway, 1025712Shsul@eecs.umich.edu // therefore no setCpuId() method is provided 1035712Shsul@eecs.umich.edu int _cpuId; 1041634SN/A 10510190Sakash.bagdia@arm.com /** Each cpu will have a socket ID that corresponds to its physical location 10610190Sakash.bagdia@arm.com * in the system. This is usually used to bucket cpu cores under single DVFS 10710190Sakash.bagdia@arm.com * domain. This information may also be required by the OS to identify the 10810190Sakash.bagdia@arm.com * cpu core grouping (as in the case of ARM via MPIDR register) 10910190Sakash.bagdia@arm.com */ 11010190Sakash.bagdia@arm.com const uint32_t _socketId; 11110190Sakash.bagdia@arm.com 1128832SAli.Saidi@ARM.com /** instruction side request id that must be placed in all requests */ 1138832SAli.Saidi@ARM.com MasterID _instMasterId; 1148832SAli.Saidi@ARM.com 1158832SAli.Saidi@ARM.com /** data side request id that must be placed in all requests */ 1168832SAli.Saidi@ARM.com MasterID _dataMasterId; 1178832SAli.Saidi@ARM.com 1189332Sdam.sunwoo@arm.com /** An intrenal representation of a task identifier within gem5. This is 1199332Sdam.sunwoo@arm.com * used so the CPU can add which taskId (which is an internal representation 1209332Sdam.sunwoo@arm.com * of the OS process ID) to each request so components in the memory system 1219332Sdam.sunwoo@arm.com * can track which process IDs are ultimately interacting with them 1229332Sdam.sunwoo@arm.com */ 1239332Sdam.sunwoo@arm.com uint32_t _taskId; 1249332Sdam.sunwoo@arm.com 1259332Sdam.sunwoo@arm.com /** The current OS process ID that is executing on this processor. This is 1269332Sdam.sunwoo@arm.com * used to generate a taskId */ 1279332Sdam.sunwoo@arm.com uint32_t _pid; 1289332Sdam.sunwoo@arm.com 1299430SAndreas.Sandberg@ARM.com /** Is the CPU switched out or active? */ 1309430SAndreas.Sandberg@ARM.com bool _switchedOut; 1319430SAndreas.Sandberg@ARM.com 1329814Sandreas.hansson@arm.com /** Cache the cache line size that we get from the system */ 1339814Sandreas.hansson@arm.com const unsigned int _cacheLineSize; 1349814Sandreas.hansson@arm.com 1351634SN/A public: 1368850Sandreas.hansson@arm.com 1378850Sandreas.hansson@arm.com /** 1388850Sandreas.hansson@arm.com * Purely virtual method that returns a reference to the data 1398850Sandreas.hansson@arm.com * port. All subclasses must implement this method. 1408850Sandreas.hansson@arm.com * 1418850Sandreas.hansson@arm.com * @return a reference to the data port 1428850Sandreas.hansson@arm.com */ 1439608Sandreas.hansson@arm.com virtual MasterPort &getDataPort() = 0; 1448850Sandreas.hansson@arm.com 1458850Sandreas.hansson@arm.com /** 1468850Sandreas.hansson@arm.com * Purely virtual method that returns a reference to the instruction 1478850Sandreas.hansson@arm.com * port. All subclasses must implement this method. 1488850Sandreas.hansson@arm.com * 1498850Sandreas.hansson@arm.com * @return a reference to the instruction port 1508850Sandreas.hansson@arm.com */ 1519608Sandreas.hansson@arm.com virtual MasterPort &getInstPort() = 0; 1528850Sandreas.hansson@arm.com 1535712Shsul@eecs.umich.edu /** Reads this CPU's ID. */ 15410110Sandreas.hansson@arm.com int cpuId() const { return _cpuId; } 1555712Shsul@eecs.umich.edu 15610190Sakash.bagdia@arm.com /** Reads this CPU's Socket ID. */ 15710190Sakash.bagdia@arm.com uint32_t socketId() const { return _socketId; } 15810190Sakash.bagdia@arm.com 1598832SAli.Saidi@ARM.com /** Reads this CPU's unique data requestor ID */ 1608832SAli.Saidi@ARM.com MasterID dataMasterId() { return _dataMasterId; } 1618832SAli.Saidi@ARM.com /** Reads this CPU's unique instruction requestor ID */ 1628832SAli.Saidi@ARM.com MasterID instMasterId() { return _instMasterId; } 1638832SAli.Saidi@ARM.com 1648850Sandreas.hansson@arm.com /** 1658926Sandreas.hansson@arm.com * Get a master port on this CPU. All CPUs have a data and 1668926Sandreas.hansson@arm.com * instruction port, and this method uses getDataPort and 1678926Sandreas.hansson@arm.com * getInstPort of the subclasses to resolve the two ports. 1688850Sandreas.hansson@arm.com * 1698850Sandreas.hansson@arm.com * @param if_name the port name 1708850Sandreas.hansson@arm.com * @param idx ignored index 1718850Sandreas.hansson@arm.com * 1728922Swilliam.wang@arm.com * @return a reference to the port with the given name 1738850Sandreas.hansson@arm.com */ 1749294Sandreas.hansson@arm.com BaseMasterPort &getMasterPort(const std::string &if_name, 1759294Sandreas.hansson@arm.com PortID idx = InvalidPortID); 1768850Sandreas.hansson@arm.com 1779332Sdam.sunwoo@arm.com /** Get cpu task id */ 1789332Sdam.sunwoo@arm.com uint32_t taskId() const { return _taskId; } 1799332Sdam.sunwoo@arm.com /** Set cpu task id */ 1809332Sdam.sunwoo@arm.com void taskId(uint32_t id) { _taskId = id; } 1819332Sdam.sunwoo@arm.com 1829332Sdam.sunwoo@arm.com uint32_t getPid() const { return _pid; } 1839332Sdam.sunwoo@arm.com void setPid(uint32_t pid) { _pid = pid; } 1849332Sdam.sunwoo@arm.com 1857914SBrad.Beckmann@amd.com inline void workItemBegin() { numWorkItemsStarted++; } 1867914SBrad.Beckmann@amd.com inline void workItemEnd() { numWorkItemsCompleted++; } 1873814Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 1883814Ssaidi@eecs.umich.edu Tick instCount() { return instCnt; } 1891634SN/A 1905664Sgblack@eecs.umich.edu TheISA::MicrocodeRom microcodeRom; 1915664Sgblack@eecs.umich.edu 1922SN/A protected: 1935704Snate@binkert.org TheISA::Interrupts *interrupts; 1942SN/A 1952SN/A public: 1965645Sgblack@eecs.umich.edu TheISA::Interrupts * 1975645Sgblack@eecs.umich.edu getInterruptController() 1985645Sgblack@eecs.umich.edu { 1995647Sgblack@eecs.umich.edu return interrupts; 2005645Sgblack@eecs.umich.edu } 2015645Sgblack@eecs.umich.edu 2025807Snate@binkert.org virtual void wakeup() = 0; 2035807Snate@binkert.org 2045807Snate@binkert.org void 2055807Snate@binkert.org postInterrupt(int int_num, int index) 2065807Snate@binkert.org { 2075807Snate@binkert.org interrupts->post(int_num, index); 2088779Sgblack@eecs.umich.edu if (FullSystem) 2098779Sgblack@eecs.umich.edu wakeup(); 2105807Snate@binkert.org } 2115807Snate@binkert.org 2125807Snate@binkert.org void 2135807Snate@binkert.org clearInterrupt(int int_num, int index) 2145807Snate@binkert.org { 2155807Snate@binkert.org interrupts->clear(int_num, index); 2165807Snate@binkert.org } 2175807Snate@binkert.org 2185807Snate@binkert.org void 2195807Snate@binkert.org clearInterrupts() 2205807Snate@binkert.org { 2215807Snate@binkert.org interrupts->clearAll(); 2225807Snate@binkert.org } 2232SN/A 2245704Snate@binkert.org bool 2255704Snate@binkert.org checkInterrupts(ThreadContext *tc) const 2265704Snate@binkert.org { 2278793Sgblack@eecs.umich.edu return FullSystem && interrupts->checkInterrupts(tc); 2285704Snate@binkert.org } 2291917SN/A 2301917SN/A class ProfileEvent : public Event 2311917SN/A { 2321917SN/A private: 2331917SN/A BaseCPU *cpu; 2345536Srstrong@hp.com Tick interval; 2351917SN/A 2361917SN/A public: 2375536Srstrong@hp.com ProfileEvent(BaseCPU *cpu, Tick interval); 2381917SN/A void process(); 2391917SN/A }; 2401917SN/A ProfileEvent *profileEvent; 2412SN/A 2422SN/A protected: 2432680Sktlim@umich.edu std::vector<ThreadContext *> threadContexts; 2442SN/A 2454776Sgblack@eecs.umich.edu Trace::InstTracer * tracer; 2464776Sgblack@eecs.umich.edu 2472SN/A public: 248393SN/A 2497764Sgblack@eecs.umich.edu // Mask to align PCs to MachInst sized boundaries 2507764Sgblack@eecs.umich.edu static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1); 2517764Sgblack@eecs.umich.edu 2524776Sgblack@eecs.umich.edu /// Provide access to the tracer pointer 2534776Sgblack@eecs.umich.edu Trace::InstTracer * getTracer() { return tracer; } 2544776Sgblack@eecs.umich.edu 25510407Smitch.hayenga@arm.com /// Notify the CPU that the indicated context is now active. 25610407Smitch.hayenga@arm.com virtual void activateContext(ThreadID thread_num) {} 257393SN/A 258393SN/A /// Notify the CPU that the indicated context is now suspended. 2598737Skoansin.tan@gmail.com virtual void suspendContext(ThreadID thread_num) {} 260393SN/A 261393SN/A /// Notify the CPU that the indicated context is now halted. 2628737Skoansin.tan@gmail.com virtual void haltContext(ThreadID thread_num) {} 2632SN/A 2644000Ssaidi@eecs.umich.edu /// Given a Thread Context pointer return the thread num 2654000Ssaidi@eecs.umich.edu int findContext(ThreadContext *tc); 2664000Ssaidi@eecs.umich.edu 2674000Ssaidi@eecs.umich.edu /// Given a thread num get tho thread context for it 2689652SAndreas.Sandberg@ARM.com virtual ThreadContext *getContext(int tn) { return threadContexts[tn]; } 2694000Ssaidi@eecs.umich.edu 27010030SAli.Saidi@ARM.com /// Get the number of thread contexts available 27110030SAli.Saidi@ARM.com unsigned numContexts() { return threadContexts.size(); } 27210030SAli.Saidi@ARM.com 2732SN/A public: 2745529Snate@binkert.org typedef BaseCPUParams Params; 2755529Snate@binkert.org const Params *params() const 2765529Snate@binkert.org { return reinterpret_cast<const Params *>(_params); } 2778876Sandreas.hansson@arm.com BaseCPU(Params *params, bool is_checker = false); 2781191SN/A virtual ~BaseCPU(); 2792SN/A 2801129SN/A virtual void init(); 2811917SN/A virtual void startup(); 2822SN/A virtual void regStats(); 2832SN/A 28410464SAndreas.Sandberg@ARM.com void regProbePoints() M5_ATTR_OVERRIDE; 28510464SAndreas.Sandberg@ARM.com 2862680Sktlim@umich.edu void registerThreadContexts(); 287180SN/A 2889254SAndreas.Sandberg@arm.com /** 2899254SAndreas.Sandberg@arm.com * Prepare for another CPU to take over execution. 2909254SAndreas.Sandberg@arm.com * 2919254SAndreas.Sandberg@arm.com * When this method exits, all internal state should have been 2929254SAndreas.Sandberg@arm.com * flushed. After the method returns, the simulator calls 2939254SAndreas.Sandberg@arm.com * takeOverFrom() on the new CPU with this CPU as its parameter. 2949254SAndreas.Sandberg@arm.com */ 2952798Sktlim@umich.edu virtual void switchOut(); 296180SN/A 2979254SAndreas.Sandberg@arm.com /** 2989254SAndreas.Sandberg@arm.com * Load the state of a CPU from the previous CPU object, invoked 2999254SAndreas.Sandberg@arm.com * on all new CPUs that are about to be switched in. 3009254SAndreas.Sandberg@arm.com * 3019254SAndreas.Sandberg@arm.com * A CPU model implementing this method is expected to initialize 3029254SAndreas.Sandberg@arm.com * its state from the old CPU and connect its memory (unless they 3039254SAndreas.Sandberg@arm.com * are already connected) to the memories connected to the old 3049254SAndreas.Sandberg@arm.com * CPU. 3059254SAndreas.Sandberg@arm.com * 3069254SAndreas.Sandberg@arm.com * @param cpu CPU to initialize read state from. 3079254SAndreas.Sandberg@arm.com */ 3089254SAndreas.Sandberg@arm.com virtual void takeOverFrom(BaseCPU *cpu); 309180SN/A 310124SN/A /** 3119446SAndreas.Sandberg@ARM.com * Flush all TLBs in the CPU. 3129446SAndreas.Sandberg@ARM.com * 3139446SAndreas.Sandberg@ARM.com * This method is mainly used to flush stale translations when 3149446SAndreas.Sandberg@ARM.com * switching CPUs. It is also exported to the Python world to 3159446SAndreas.Sandberg@ARM.com * allow it to request a TLB flush after draining the CPU to make 3169446SAndreas.Sandberg@ARM.com * it easier to compare traces when debugging 3179446SAndreas.Sandberg@ARM.com * handover/checkpointing. 3189446SAndreas.Sandberg@ARM.com */ 3199446SAndreas.Sandberg@ARM.com void flushTLBs(); 3209446SAndreas.Sandberg@ARM.com 3219446SAndreas.Sandberg@ARM.com /** 3229430SAndreas.Sandberg@ARM.com * Determine if the CPU is switched out. 3239430SAndreas.Sandberg@ARM.com * 3249430SAndreas.Sandberg@ARM.com * @return True if the CPU is switched out, false otherwise. 3259430SAndreas.Sandberg@ARM.com */ 3269430SAndreas.Sandberg@ARM.com bool switchedOut() const { return _switchedOut; } 3279430SAndreas.Sandberg@ARM.com 3289430SAndreas.Sandberg@ARM.com /** 3299523SAndreas.Sandberg@ARM.com * Verify that the system is in a memory mode supported by the 3309523SAndreas.Sandberg@ARM.com * CPU. 3319523SAndreas.Sandberg@ARM.com * 3329523SAndreas.Sandberg@ARM.com * Implementations are expected to query the system for the 3339523SAndreas.Sandberg@ARM.com * current memory mode and ensure that it is what the CPU model 3349523SAndreas.Sandberg@ARM.com * expects. If the check fails, the implementation should 3359523SAndreas.Sandberg@ARM.com * terminate the simulation using fatal(). 3369523SAndreas.Sandberg@ARM.com */ 3379523SAndreas.Sandberg@ARM.com virtual void verifyMemoryMode() const { }; 3389523SAndreas.Sandberg@ARM.com 3399523SAndreas.Sandberg@ARM.com /** 340124SN/A * Number of threads we're actually simulating (<= SMT_MAX_THREADS). 341124SN/A * This is a constant for the duration of the simulation. 342124SN/A */ 3436221Snate@binkert.org ThreadID numThreads; 3442SN/A 345124SN/A /** 346124SN/A * Vector of per-thread instruction-based event queues. Used for 347124SN/A * scheduling events based on number of instructions committed by 348124SN/A * a particular thread. 349124SN/A */ 350503SN/A EventQueue **comInstEventQueue; 3512SN/A 352124SN/A /** 353124SN/A * Vector of per-thread load-based event queues. Used for 354124SN/A * scheduling events based on number of loads committed by 355124SN/A *a particular thread. 356124SN/A */ 357124SN/A EventQueue **comLoadEventQueue; 358124SN/A 3592SN/A System *system; 360921SN/A 361921SN/A /** 3629814Sandreas.hansson@arm.com * Get the cache line size of the system. 3639814Sandreas.hansson@arm.com */ 3649814Sandreas.hansson@arm.com inline unsigned int cacheLineSize() const { return _cacheLineSize; } 3659814Sandreas.hansson@arm.com 3669814Sandreas.hansson@arm.com /** 367921SN/A * Serialize this object to the given output stream. 3689448SAndreas.Sandberg@ARM.com * 3699448SAndreas.Sandberg@ARM.com * @note CPU models should normally overload the serializeThread() 3709448SAndreas.Sandberg@ARM.com * method instead of the serialize() method as this provides a 3719448SAndreas.Sandberg@ARM.com * uniform data format for all CPU models and promotes better code 3729448SAndreas.Sandberg@ARM.com * reuse. 3739448SAndreas.Sandberg@ARM.com * 374921SN/A * @param os The stream to serialize to. 375921SN/A */ 376921SN/A virtual void serialize(std::ostream &os); 377921SN/A 378921SN/A /** 379921SN/A * Reconstruct the state of this object from a checkpoint. 3809448SAndreas.Sandberg@ARM.com * 3819448SAndreas.Sandberg@ARM.com * @note CPU models should normally overload the 3829448SAndreas.Sandberg@ARM.com * unserializeThread() method instead of the unserialize() method 3839448SAndreas.Sandberg@ARM.com * as this provides a uniform data format for all CPU models and 3849448SAndreas.Sandberg@ARM.com * promotes better code reuse. 3859448SAndreas.Sandberg@ARM.com 386921SN/A * @param cp The checkpoint use. 3879448SAndreas.Sandberg@ARM.com * @param section The section name of this object. 388921SN/A */ 389921SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion); 390921SN/A 391124SN/A /** 3929448SAndreas.Sandberg@ARM.com * Serialize a single thread. 3939448SAndreas.Sandberg@ARM.com * 3949448SAndreas.Sandberg@ARM.com * @param os The stream to serialize to. 3959448SAndreas.Sandberg@ARM.com * @param tid ID of the current thread. 3969448SAndreas.Sandberg@ARM.com */ 3979448SAndreas.Sandberg@ARM.com virtual void serializeThread(std::ostream &os, ThreadID tid) {}; 3989448SAndreas.Sandberg@ARM.com 3999448SAndreas.Sandberg@ARM.com /** 4009448SAndreas.Sandberg@ARM.com * Unserialize one thread. 4019448SAndreas.Sandberg@ARM.com * 4029448SAndreas.Sandberg@ARM.com * @param cp The checkpoint use. 4039448SAndreas.Sandberg@ARM.com * @param section The section name of this thread. 4049448SAndreas.Sandberg@ARM.com * @param tid ID of the current thread. 4059448SAndreas.Sandberg@ARM.com */ 4069448SAndreas.Sandberg@ARM.com virtual void unserializeThread(Checkpoint *cp, const std::string §ion, 4079448SAndreas.Sandberg@ARM.com ThreadID tid) {}; 4089448SAndreas.Sandberg@ARM.com 4098834Satgutier@umich.edu virtual Counter totalInsts() const = 0; 4108834Satgutier@umich.edu 4118834Satgutier@umich.edu virtual Counter totalOps() const = 0; 412707SN/A 4139749Sandreas@sandberg.pp.se /** 4149749Sandreas@sandberg.pp.se * Schedule an event that exits the simulation loops after a 4159749Sandreas@sandberg.pp.se * predefined number of instructions. 4169749Sandreas@sandberg.pp.se * 4179749Sandreas@sandberg.pp.se * This method is usually called from the configuration script to 4189749Sandreas@sandberg.pp.se * get an exit event some time in the future. It is typically used 4199749Sandreas@sandberg.pp.se * when the script wants to simulate for a specific number of 4209749Sandreas@sandberg.pp.se * instructions rather than ticks. 4219749Sandreas@sandberg.pp.se * 4229749Sandreas@sandberg.pp.se * @param tid Thread monitor. 4239749Sandreas@sandberg.pp.se * @param insts Number of instructions into the future. 4249749Sandreas@sandberg.pp.se * @param cause Cause to signal in the exit event. 4259749Sandreas@sandberg.pp.se */ 4269749Sandreas@sandberg.pp.se void scheduleInstStop(ThreadID tid, Counter insts, const char *cause); 4279749Sandreas@sandberg.pp.se 4289749Sandreas@sandberg.pp.se /** 4299749Sandreas@sandberg.pp.se * Schedule an event that exits the simulation loops after a 4309749Sandreas@sandberg.pp.se * predefined number of load operations. 4319749Sandreas@sandberg.pp.se * 4329749Sandreas@sandberg.pp.se * This method is usually called from the configuration script to 4339749Sandreas@sandberg.pp.se * get an exit event some time in the future. It is typically used 4349749Sandreas@sandberg.pp.se * when the script wants to simulate for a specific number of 4359749Sandreas@sandberg.pp.se * loads rather than ticks. 4369749Sandreas@sandberg.pp.se * 4379749Sandreas@sandberg.pp.se * @param tid Thread monitor. 4389749Sandreas@sandberg.pp.se * @param loads Number of load instructions into the future. 4399749Sandreas@sandberg.pp.se * @param cause Cause to signal in the exit event. 4409749Sandreas@sandberg.pp.se */ 4419749Sandreas@sandberg.pp.se void scheduleLoadStop(ThreadID tid, Counter loads, const char *cause); 4429749Sandreas@sandberg.pp.se 44310464SAndreas.Sandberg@ARM.com public: 44410464SAndreas.Sandberg@ARM.com /** 44510464SAndreas.Sandberg@ARM.com * @{ 44610464SAndreas.Sandberg@ARM.com * @name PMU Probe points. 44710464SAndreas.Sandberg@ARM.com */ 44810464SAndreas.Sandberg@ARM.com 44910464SAndreas.Sandberg@ARM.com /** 45010464SAndreas.Sandberg@ARM.com * Helper method to trigger PMU probes for a committed 45110464SAndreas.Sandberg@ARM.com * instruction. 45210464SAndreas.Sandberg@ARM.com * 45310464SAndreas.Sandberg@ARM.com * @param inst Instruction that just committed 45410464SAndreas.Sandberg@ARM.com */ 45510464SAndreas.Sandberg@ARM.com virtual void probeInstCommit(const StaticInstPtr &inst); 45610464SAndreas.Sandberg@ARM.com 45710464SAndreas.Sandberg@ARM.com /** 45810464SAndreas.Sandberg@ARM.com * Helper method to instantiate probe points belonging to this 45910464SAndreas.Sandberg@ARM.com * object. 46010464SAndreas.Sandberg@ARM.com * 46110464SAndreas.Sandberg@ARM.com * @param name Name of the probe point. 46210464SAndreas.Sandberg@ARM.com * @return A unique_ptr to the new probe point. 46310464SAndreas.Sandberg@ARM.com */ 46410464SAndreas.Sandberg@ARM.com ProbePoints::PMUUPtr pmuProbePoint(const char *name); 46510464SAndreas.Sandberg@ARM.com 46610464SAndreas.Sandberg@ARM.com /** CPU cycle counter */ 46710464SAndreas.Sandberg@ARM.com ProbePoints::PMUUPtr ppCycles; 46810464SAndreas.Sandberg@ARM.com 46910464SAndreas.Sandberg@ARM.com /** 47010464SAndreas.Sandberg@ARM.com * Instruction commit probe point. 47110464SAndreas.Sandberg@ARM.com * 47210464SAndreas.Sandberg@ARM.com * This probe point is triggered whenever one or more instructions 47310464SAndreas.Sandberg@ARM.com * are committed. It is normally triggered once for every 47410464SAndreas.Sandberg@ARM.com * instruction. However, CPU models committing bundles of 47510464SAndreas.Sandberg@ARM.com * instructions may call notify once for the entire bundle. 47610464SAndreas.Sandberg@ARM.com */ 47710464SAndreas.Sandberg@ARM.com ProbePoints::PMUUPtr ppRetiredInsts; 47810464SAndreas.Sandberg@ARM.com 47910464SAndreas.Sandberg@ARM.com /** Retired load instructions */ 48010464SAndreas.Sandberg@ARM.com ProbePoints::PMUUPtr ppRetiredLoads; 48110464SAndreas.Sandberg@ARM.com /** Retired store instructions */ 48210464SAndreas.Sandberg@ARM.com ProbePoints::PMUUPtr ppRetiredStores; 48310464SAndreas.Sandberg@ARM.com 48410464SAndreas.Sandberg@ARM.com /** Retired branches (any type) */ 48510464SAndreas.Sandberg@ARM.com ProbePoints::PMUUPtr ppRetiredBranches; 48610464SAndreas.Sandberg@ARM.com 48710464SAndreas.Sandberg@ARM.com /** @} */ 48810464SAndreas.Sandberg@ARM.com 48910464SAndreas.Sandberg@ARM.com 49010464SAndreas.Sandberg@ARM.com 4911191SN/A // Function tracing 4921191SN/A private: 4931191SN/A bool functionTracingEnabled; 4941191SN/A std::ostream *functionTraceStream; 4951191SN/A Addr currentFunctionStart; 4961191SN/A Addr currentFunctionEnd; 4971191SN/A Tick functionEntryTick; 4981191SN/A void enableFunctionTrace(); 4991191SN/A void traceFunctionsInternal(Addr pc); 5001191SN/A 5018662SAli.Saidi@ARM.com private: 5028662SAli.Saidi@ARM.com static std::vector<BaseCPU *> cpuList; //!< Static global cpu list 5038662SAli.Saidi@ARM.com 5048662SAli.Saidi@ARM.com public: 5051191SN/A void traceFunctions(Addr pc) 5061191SN/A { 5071191SN/A if (functionTracingEnabled) 5081191SN/A traceFunctionsInternal(pc); 5091191SN/A } 5101191SN/A 5112SN/A static int numSimulatedCPUs() { return cpuList.size(); } 5128834Satgutier@umich.edu static Counter numSimulatedInsts() 513707SN/A { 514707SN/A Counter total = 0; 515707SN/A 516707SN/A int size = cpuList.size(); 517707SN/A for (int i = 0; i < size; ++i) 5188834Satgutier@umich.edu total += cpuList[i]->totalInsts(); 5198834Satgutier@umich.edu 5208834Satgutier@umich.edu return total; 5218834Satgutier@umich.edu } 5228834Satgutier@umich.edu 5238834Satgutier@umich.edu static Counter numSimulatedOps() 5248834Satgutier@umich.edu { 5258834Satgutier@umich.edu Counter total = 0; 5268834Satgutier@umich.edu 5278834Satgutier@umich.edu int size = cpuList.size(); 5288834Satgutier@umich.edu for (int i = 0; i < size; ++i) 5298834Satgutier@umich.edu total += cpuList[i]->totalOps(); 530707SN/A 531707SN/A return total; 532707SN/A } 533707SN/A 534707SN/A public: 535707SN/A // Number of CPU cycles simulated 5365999Snate@binkert.org Stats::Scalar numCycles; 5377914SBrad.Beckmann@amd.com Stats::Scalar numWorkItemsStarted; 5387914SBrad.Beckmann@amd.com Stats::Scalar numWorkItemsCompleted; 5392SN/A}; 5402SN/A 5419850Sandreas.hansson@arm.com#endif // THE_ISA == NULL_ISA 5429850Sandreas.hansson@arm.com 5431717SN/A#endif // __CPU_BASE_HH__ 544