base.hh revision 10464
1/* 2 * Copyright (c) 2011-2013 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2002-2005 The Regents of The University of Michigan 15 * Copyright (c) 2011 Regents of the University of California 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Steve Reinhardt 42 * Nathan Binkert 43 * Rick Strong 44 */ 45 46#ifndef __CPU_BASE_HH__ 47#define __CPU_BASE_HH__ 48 49#include <vector> 50 51// Before we do anything else, check if this build is the NULL ISA, 52// and if so stop here 53#include "config/the_isa.hh" 54#if THE_ISA == NULL_ISA 55#include "arch/null/cpu_dummy.hh" 56#else 57#include "arch/interrupts.hh" 58#include "arch/isa_traits.hh" 59#include "arch/microcode_rom.hh" 60#include "base/statistics.hh" 61#include "mem/mem_object.hh" 62#include "sim/eventq.hh" 63#include "sim/full_system.hh" 64#include "sim/insttracer.hh" 65#include "sim/probe/pmu.hh" 66#include "sim/system.hh" 67 68struct BaseCPUParams; 69class CheckerCPU; 70class ThreadContext; 71 72class CPUProgressEvent : public Event 73{ 74 protected: 75 Tick _interval; 76 Counter lastNumInst; 77 BaseCPU *cpu; 78 bool _repeatEvent; 79 80 public: 81 CPUProgressEvent(BaseCPU *_cpu, Tick ival = 0); 82 83 void process(); 84 85 void interval(Tick ival) { _interval = ival; } 86 Tick interval() { return _interval; } 87 88 void repeatEvent(bool repeat) { _repeatEvent = repeat; } 89 90 virtual const char *description() const; 91}; 92 93class BaseCPU : public MemObject 94{ 95 protected: 96 97 // @todo remove me after debugging with legion done 98 Tick instCnt; 99 // every cpu has an id, put it in the base cpu 100 // Set at initialization, only time a cpuId might change is during a 101 // takeover (which should be done from within the BaseCPU anyway, 102 // therefore no setCpuId() method is provided 103 int _cpuId; 104 105 /** Each cpu will have a socket ID that corresponds to its physical location 106 * in the system. This is usually used to bucket cpu cores under single DVFS 107 * domain. This information may also be required by the OS to identify the 108 * cpu core grouping (as in the case of ARM via MPIDR register) 109 */ 110 const uint32_t _socketId; 111 112 /** instruction side request id that must be placed in all requests */ 113 MasterID _instMasterId; 114 115 /** data side request id that must be placed in all requests */ 116 MasterID _dataMasterId; 117 118 /** An intrenal representation of a task identifier within gem5. This is 119 * used so the CPU can add which taskId (which is an internal representation 120 * of the OS process ID) to each request so components in the memory system 121 * can track which process IDs are ultimately interacting with them 122 */ 123 uint32_t _taskId; 124 125 /** The current OS process ID that is executing on this processor. This is 126 * used to generate a taskId */ 127 uint32_t _pid; 128 129 /** Is the CPU switched out or active? */ 130 bool _switchedOut; 131 132 /** Cache the cache line size that we get from the system */ 133 const unsigned int _cacheLineSize; 134 135 public: 136 137 /** 138 * Purely virtual method that returns a reference to the data 139 * port. All subclasses must implement this method. 140 * 141 * @return a reference to the data port 142 */ 143 virtual MasterPort &getDataPort() = 0; 144 145 /** 146 * Purely virtual method that returns a reference to the instruction 147 * port. All subclasses must implement this method. 148 * 149 * @return a reference to the instruction port 150 */ 151 virtual MasterPort &getInstPort() = 0; 152 153 /** Reads this CPU's ID. */ 154 int cpuId() const { return _cpuId; } 155 156 /** Reads this CPU's Socket ID. */ 157 uint32_t socketId() const { return _socketId; } 158 159 /** Reads this CPU's unique data requestor ID */ 160 MasterID dataMasterId() { return _dataMasterId; } 161 /** Reads this CPU's unique instruction requestor ID */ 162 MasterID instMasterId() { return _instMasterId; } 163 164 /** 165 * Get a master port on this CPU. All CPUs have a data and 166 * instruction port, and this method uses getDataPort and 167 * getInstPort of the subclasses to resolve the two ports. 168 * 169 * @param if_name the port name 170 * @param idx ignored index 171 * 172 * @return a reference to the port with the given name 173 */ 174 BaseMasterPort &getMasterPort(const std::string &if_name, 175 PortID idx = InvalidPortID); 176 177 /** Get cpu task id */ 178 uint32_t taskId() const { return _taskId; } 179 /** Set cpu task id */ 180 void taskId(uint32_t id) { _taskId = id; } 181 182 uint32_t getPid() const { return _pid; } 183 void setPid(uint32_t pid) { _pid = pid; } 184 185 inline void workItemBegin() { numWorkItemsStarted++; } 186 inline void workItemEnd() { numWorkItemsCompleted++; } 187 // @todo remove me after debugging with legion done 188 Tick instCount() { return instCnt; } 189 190 TheISA::MicrocodeRom microcodeRom; 191 192 protected: 193 TheISA::Interrupts *interrupts; 194 195 public: 196 TheISA::Interrupts * 197 getInterruptController() 198 { 199 return interrupts; 200 } 201 202 virtual void wakeup() = 0; 203 204 void 205 postInterrupt(int int_num, int index) 206 { 207 interrupts->post(int_num, index); 208 if (FullSystem) 209 wakeup(); 210 } 211 212 void 213 clearInterrupt(int int_num, int index) 214 { 215 interrupts->clear(int_num, index); 216 } 217 218 void 219 clearInterrupts() 220 { 221 interrupts->clearAll(); 222 } 223 224 bool 225 checkInterrupts(ThreadContext *tc) const 226 { 227 return FullSystem && interrupts->checkInterrupts(tc); 228 } 229 230 class ProfileEvent : public Event 231 { 232 private: 233 BaseCPU *cpu; 234 Tick interval; 235 236 public: 237 ProfileEvent(BaseCPU *cpu, Tick interval); 238 void process(); 239 }; 240 ProfileEvent *profileEvent; 241 242 protected: 243 std::vector<ThreadContext *> threadContexts; 244 245 Trace::InstTracer * tracer; 246 247 public: 248 249 // Mask to align PCs to MachInst sized boundaries 250 static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1); 251 252 /// Provide access to the tracer pointer 253 Trace::InstTracer * getTracer() { return tracer; } 254 255 /// Notify the CPU that the indicated context is now active. 256 virtual void activateContext(ThreadID thread_num) {} 257 258 /// Notify the CPU that the indicated context is now suspended. 259 virtual void suspendContext(ThreadID thread_num) {} 260 261 /// Notify the CPU that the indicated context is now halted. 262 virtual void haltContext(ThreadID thread_num) {} 263 264 /// Given a Thread Context pointer return the thread num 265 int findContext(ThreadContext *tc); 266 267 /// Given a thread num get tho thread context for it 268 virtual ThreadContext *getContext(int tn) { return threadContexts[tn]; } 269 270 /// Get the number of thread contexts available 271 unsigned numContexts() { return threadContexts.size(); } 272 273 public: 274 typedef BaseCPUParams Params; 275 const Params *params() const 276 { return reinterpret_cast<const Params *>(_params); } 277 BaseCPU(Params *params, bool is_checker = false); 278 virtual ~BaseCPU(); 279 280 virtual void init(); 281 virtual void startup(); 282 virtual void regStats(); 283 284 void regProbePoints() M5_ATTR_OVERRIDE; 285 286 void registerThreadContexts(); 287 288 /** 289 * Prepare for another CPU to take over execution. 290 * 291 * When this method exits, all internal state should have been 292 * flushed. After the method returns, the simulator calls 293 * takeOverFrom() on the new CPU with this CPU as its parameter. 294 */ 295 virtual void switchOut(); 296 297 /** 298 * Load the state of a CPU from the previous CPU object, invoked 299 * on all new CPUs that are about to be switched in. 300 * 301 * A CPU model implementing this method is expected to initialize 302 * its state from the old CPU and connect its memory (unless they 303 * are already connected) to the memories connected to the old 304 * CPU. 305 * 306 * @param cpu CPU to initialize read state from. 307 */ 308 virtual void takeOverFrom(BaseCPU *cpu); 309 310 /** 311 * Flush all TLBs in the CPU. 312 * 313 * This method is mainly used to flush stale translations when 314 * switching CPUs. It is also exported to the Python world to 315 * allow it to request a TLB flush after draining the CPU to make 316 * it easier to compare traces when debugging 317 * handover/checkpointing. 318 */ 319 void flushTLBs(); 320 321 /** 322 * Determine if the CPU is switched out. 323 * 324 * @return True if the CPU is switched out, false otherwise. 325 */ 326 bool switchedOut() const { return _switchedOut; } 327 328 /** 329 * Verify that the system is in a memory mode supported by the 330 * CPU. 331 * 332 * Implementations are expected to query the system for the 333 * current memory mode and ensure that it is what the CPU model 334 * expects. If the check fails, the implementation should 335 * terminate the simulation using fatal(). 336 */ 337 virtual void verifyMemoryMode() const { }; 338 339 /** 340 * Number of threads we're actually simulating (<= SMT_MAX_THREADS). 341 * This is a constant for the duration of the simulation. 342 */ 343 ThreadID numThreads; 344 345 /** 346 * Vector of per-thread instruction-based event queues. Used for 347 * scheduling events based on number of instructions committed by 348 * a particular thread. 349 */ 350 EventQueue **comInstEventQueue; 351 352 /** 353 * Vector of per-thread load-based event queues. Used for 354 * scheduling events based on number of loads committed by 355 *a particular thread. 356 */ 357 EventQueue **comLoadEventQueue; 358 359 System *system; 360 361 /** 362 * Get the cache line size of the system. 363 */ 364 inline unsigned int cacheLineSize() const { return _cacheLineSize; } 365 366 /** 367 * Serialize this object to the given output stream. 368 * 369 * @note CPU models should normally overload the serializeThread() 370 * method instead of the serialize() method as this provides a 371 * uniform data format for all CPU models and promotes better code 372 * reuse. 373 * 374 * @param os The stream to serialize to. 375 */ 376 virtual void serialize(std::ostream &os); 377 378 /** 379 * Reconstruct the state of this object from a checkpoint. 380 * 381 * @note CPU models should normally overload the 382 * unserializeThread() method instead of the unserialize() method 383 * as this provides a uniform data format for all CPU models and 384 * promotes better code reuse. 385 386 * @param cp The checkpoint use. 387 * @param section The section name of this object. 388 */ 389 virtual void unserialize(Checkpoint *cp, const std::string §ion); 390 391 /** 392 * Serialize a single thread. 393 * 394 * @param os The stream to serialize to. 395 * @param tid ID of the current thread. 396 */ 397 virtual void serializeThread(std::ostream &os, ThreadID tid) {}; 398 399 /** 400 * Unserialize one thread. 401 * 402 * @param cp The checkpoint use. 403 * @param section The section name of this thread. 404 * @param tid ID of the current thread. 405 */ 406 virtual void unserializeThread(Checkpoint *cp, const std::string §ion, 407 ThreadID tid) {}; 408 409 virtual Counter totalInsts() const = 0; 410 411 virtual Counter totalOps() const = 0; 412 413 /** 414 * Schedule an event that exits the simulation loops after a 415 * predefined number of instructions. 416 * 417 * This method is usually called from the configuration script to 418 * get an exit event some time in the future. It is typically used 419 * when the script wants to simulate for a specific number of 420 * instructions rather than ticks. 421 * 422 * @param tid Thread monitor. 423 * @param insts Number of instructions into the future. 424 * @param cause Cause to signal in the exit event. 425 */ 426 void scheduleInstStop(ThreadID tid, Counter insts, const char *cause); 427 428 /** 429 * Schedule an event that exits the simulation loops after a 430 * predefined number of load operations. 431 * 432 * This method is usually called from the configuration script to 433 * get an exit event some time in the future. It is typically used 434 * when the script wants to simulate for a specific number of 435 * loads rather than ticks. 436 * 437 * @param tid Thread monitor. 438 * @param loads Number of load instructions into the future. 439 * @param cause Cause to signal in the exit event. 440 */ 441 void scheduleLoadStop(ThreadID tid, Counter loads, const char *cause); 442 443 public: 444 /** 445 * @{ 446 * @name PMU Probe points. 447 */ 448 449 /** 450 * Helper method to trigger PMU probes for a committed 451 * instruction. 452 * 453 * @param inst Instruction that just committed 454 */ 455 virtual void probeInstCommit(const StaticInstPtr &inst); 456 457 /** 458 * Helper method to instantiate probe points belonging to this 459 * object. 460 * 461 * @param name Name of the probe point. 462 * @return A unique_ptr to the new probe point. 463 */ 464 ProbePoints::PMUUPtr pmuProbePoint(const char *name); 465 466 /** CPU cycle counter */ 467 ProbePoints::PMUUPtr ppCycles; 468 469 /** 470 * Instruction commit probe point. 471 * 472 * This probe point is triggered whenever one or more instructions 473 * are committed. It is normally triggered once for every 474 * instruction. However, CPU models committing bundles of 475 * instructions may call notify once for the entire bundle. 476 */ 477 ProbePoints::PMUUPtr ppRetiredInsts; 478 479 /** Retired load instructions */ 480 ProbePoints::PMUUPtr ppRetiredLoads; 481 /** Retired store instructions */ 482 ProbePoints::PMUUPtr ppRetiredStores; 483 484 /** Retired branches (any type) */ 485 ProbePoints::PMUUPtr ppRetiredBranches; 486 487 /** @} */ 488 489 490 491 // Function tracing 492 private: 493 bool functionTracingEnabled; 494 std::ostream *functionTraceStream; 495 Addr currentFunctionStart; 496 Addr currentFunctionEnd; 497 Tick functionEntryTick; 498 void enableFunctionTrace(); 499 void traceFunctionsInternal(Addr pc); 500 501 private: 502 static std::vector<BaseCPU *> cpuList; //!< Static global cpu list 503 504 public: 505 void traceFunctions(Addr pc) 506 { 507 if (functionTracingEnabled) 508 traceFunctionsInternal(pc); 509 } 510 511 static int numSimulatedCPUs() { return cpuList.size(); } 512 static Counter numSimulatedInsts() 513 { 514 Counter total = 0; 515 516 int size = cpuList.size(); 517 for (int i = 0; i < size; ++i) 518 total += cpuList[i]->totalInsts(); 519 520 return total; 521 } 522 523 static Counter numSimulatedOps() 524 { 525 Counter total = 0; 526 527 int size = cpuList.size(); 528 for (int i = 0; i < size; ++i) 529 total += cpuList[i]->totalOps(); 530 531 return total; 532 } 533 534 public: 535 // Number of CPU cycles simulated 536 Stats::Scalar numCycles; 537 Stats::Scalar numWorkItemsStarted; 538 Stats::Scalar numWorkItemsCompleted; 539}; 540 541#endif // THE_ISA == NULL_ISA 542 543#endif // __CPU_BASE_HH__ 544