base.cc revision 605
12SN/A/* 212276Sanouk.vanlaer@arm.com * Copyright (c) 2003 The Regents of The University of Michigan 38707Sandreas.hansson@arm.com * All rights reserved. 48707Sandreas.hansson@arm.com * 58707Sandreas.hansson@arm.com * Redistribution and use in source and binary forms, with or without 68707Sandreas.hansson@arm.com * modification, are permitted provided that the following conditions are 78707Sandreas.hansson@arm.com * met: redistributions of source code must retain the above copyright 88707Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer; 98707Sandreas.hansson@arm.com * redistributions in binary form must reproduce the above copyright 108707Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer in the 118707Sandreas.hansson@arm.com * documentation and/or other materials provided with the distribution; 128707Sandreas.hansson@arm.com * neither the name of the copyright holders nor the names of its 138707Sandreas.hansson@arm.com * contributors may be used to endorse or promote products derived from 141762SN/A * this software without specific prior written permission. 157897Shestness@cs.utexas.edu * 169983Sstever@gmail.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 179983Sstever@gmail.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272SN/A */ 282SN/A 292SN/A#include <string> 302SN/A#include <sstream> 312SN/A#include <iostream> 322SN/A 332SN/A#include "cpu/base_cpu.hh" 342SN/A#include "base/cprintf.hh" 352SN/A#include "cpu/exec_context.hh" 362SN/A#include "base/misc.hh" 372SN/A#include "sim/param.hh" 382SN/A#include "sim/sim_events.hh" 392SN/A 402SN/Ausing namespace std; 412SN/A 422665Ssaidi@eecs.umich.eduvector<BaseCPU *> BaseCPU::cpuList; 432665Ssaidi@eecs.umich.edu 442665Ssaidi@eecs.umich.edu// This variable reflects the max number of threads in any CPU. Be 457897Shestness@cs.utexas.edu// careful to only use it once all the CPUs that you care about have 462SN/A// been initialized 472SN/Aint maxThreadsPerCPU = 1; 4811793Sbrandon.potter@amd.com 4911793Sbrandon.potter@amd.com#ifdef FULL_SYSTEM 501388SN/ABaseCPU::BaseCPU(const string &_name, int _number_of_threads, 518229Snate@binkert.org Counter max_insts_any_thread, 522SN/A Counter max_insts_all_threads, 532SN/A Counter max_loads_any_thread, 5412406Sgabeblack@google.com Counter max_loads_all_threads, 5511793Sbrandon.potter@amd.com System *_system, Tick freq) 568229Snate@binkert.org : SimObject(_name), frequency(freq), 5712334Sgabeblack@google.com number_of_threads(_number_of_threads), system(_system) 581388SN/A#else 595529Snate@binkert.orgBaseCPU::BaseCPU(const string &_name, int _number_of_threads, 6010529Smorr@cs.wisc.edu Counter max_insts_any_thread, 612651Ssaidi@eecs.umich.edu Counter max_insts_all_threads, 628229Snate@binkert.org Counter max_loads_any_thread, 632680Sktlim@umich.edu Counter max_loads_all_threads) 6410529Smorr@cs.wisc.edu : SimObject(_name), number_of_threads(_number_of_threads) 658232Snate@binkert.org#endif 6610529Smorr@cs.wisc.edu{ 675529Snate@binkert.org // add self to global list of CPUs 6811526Sdavid.guillen@arm.com cpuList.push_back(this); 698779Sgblack@eecs.umich.edu 702190SN/A if (number_of_threads > maxThreadsPerCPU) 7156SN/A maxThreadsPerCPU = number_of_threads; 728229Snate@binkert.org 732190SN/A // allocate per-thread instruction-based event queues 742SN/A comInstEventQueue = new (EventQueue *)[number_of_threads]; 752359SN/A for (int i = 0; i < number_of_threads; ++i) 762359SN/A comInstEventQueue[i] = new EventQueue("instruction-based event queue"); 772359SN/A 782SN/A // 792SN/A // set up instruction-count-based termination events, if any 802SN/A // 812SN/A if (max_insts_any_thread != 0) 822SN/A for (int i = 0; i < number_of_threads; ++i) 832SN/A new SimExitEvent(comInstEventQueue[i], max_insts_any_thread, 842SN/A "a thread reached the max instruction count"); 852SN/A 862SN/A if (max_insts_all_threads != 0) { 875606Snate@binkert.org // allocate & initialize shared downcounter: each event will 886144Sksewell@umich.edu // decrement this when triggered; simulation will terminate 896144Sksewell@umich.edu // when counter reaches 0 903126Sktlim@umich.edu int *counter = new int; 916144Sksewell@umich.edu *counter = number_of_threads; 927823Ssteve.reinhardt@amd.com for (int i = 0; i < number_of_threads; ++i) 933126Sktlim@umich.edu new CountedExitEvent(comInstEventQueue[i], 943126Sktlim@umich.edu "all threads reached the max instruction count", 952356SN/A max_insts_all_threads, *counter); 962356SN/A } 972356SN/A 988834Satgutier@umich.edu // allocate per-thread load-based event queues 9910786Smalek.musleh@gmail.com comLoadEventQueue = new (EventQueue *)[number_of_threads]; 10010786Smalek.musleh@gmail.com for (int i = 0; i < number_of_threads; ++i) 10110786Smalek.musleh@gmail.com comLoadEventQueue[i] = new EventQueue("load-based event queue"); 10210786Smalek.musleh@gmail.com 10311321Ssteve.reinhardt@amd.com // 10410786Smalek.musleh@gmail.com // set up instruction-count-based termination events, if any 10510786Smalek.musleh@gmail.com // 10610786Smalek.musleh@gmail.com if (max_loads_any_thread != 0) 1072356SN/A for (int i = 0; i < number_of_threads; ++i) 1089179Sandreas.hansson@arm.com new SimExitEvent(comLoadEventQueue[i], max_loads_any_thread, 1092367SN/A "a thread reached the max load count"); 1106144Sksewell@umich.edu 1116144Sksewell@umich.edu if (max_loads_all_threads != 0) { 1126144Sksewell@umich.edu // allocate & initialize shared downcounter: each event will 1132356SN/A // decrement this when triggered; simulation will terminate 1142367SN/A // when counter reaches 0 1156144Sksewell@umich.edu int *counter = new int; 1167823Ssteve.reinhardt@amd.com *counter = number_of_threads; 1176144Sksewell@umich.edu for (int i = 0; i < number_of_threads; ++i) 1182367SN/A new CountedExitEvent(comLoadEventQueue[i], 1192356SN/A "all threads reached the max load count", 1202356SN/A max_loads_all_threads, *counter); 1212356SN/A } 1222356SN/A 1235336Shines@cs.fsu.edu#ifdef FULL_SYSTEM 1242356SN/A memset(interrupts, 0, sizeof(interrupts)); 1254873Sstever@eecs.umich.edu intstatus = 0; 1262356SN/A#endif 1272356SN/A} 1288876Sandreas.hansson@arm.com 12910190Sakash.bagdia@arm.com 13012680Sgiacomo.travaglini@arm.comvoid 13112680Sgiacomo.travaglini@arm.comBaseCPU::regStats() 13211050Sandreas.hansson@arm.com{ 1339814Sandreas.hansson@arm.com int size = execContexts.size(); 1349220Shestness@cs.wisc.edu if (size > 1) { 13510529Smorr@cs.wisc.edu for (int i = 0; i < size; ++i) { 13612284Sjose.marinho@arm.com stringstream namestr; 13710537Sandreas.hansson@arm.com ccprintf(namestr, "%s.ctx%d", name(), i); 13810537Sandreas.hansson@arm.com execContexts[i]->regStats(namestr.str()); 13911877Sbrandon.potter@amd.com } 14012276Sanouk.vanlaer@arm.com } else if (size == 1) 14112276Sanouk.vanlaer@arm.com execContexts[0]->regStats(name()); 14212277Sjose.marinho@arm.com} 14312276Sanouk.vanlaer@arm.com 1442SN/A 1455712Shsul@eecs.umich.eduvoid 1465712Shsul@eecs.umich.eduBaseCPU::registerExecContexts() 1475712Shsul@eecs.umich.edu{ 1485712Shsul@eecs.umich.edu for (int i = 0; i < execContexts.size(); ++i) { 1495712Shsul@eecs.umich.edu ExecContext *xc = execContexts[i]; 1502SN/A int cpu_id; 1512SN/A 1522SN/A#ifdef FULL_SYSTEM 15310190Sakash.bagdia@arm.com cpu_id = system->registerExecContext(xc); 15410190Sakash.bagdia@arm.com#else 1555712Shsul@eecs.umich.edu cpu_id = xc->process->registerExecContext(xc); 1566221Snate@binkert.org#endif 1576221Snate@binkert.org 1582SN/A xc->cpu_id = cpu_id; 1592SN/A } 1606221Snate@binkert.org} 1616221Snate@binkert.org 1626221Snate@binkert.org 1636221Snate@binkert.orgvoid 1642SN/ABaseCPU::switchOut() 1652SN/A{ 1662SN/A // default: do nothing 1672SN/A} 1685606Snate@binkert.org 1695606Snate@binkert.orgvoid 1709749Sandreas@sandberg.pp.seBaseCPU::takeOverFrom(BaseCPU *oldCPU) 1719749Sandreas@sandberg.pp.se{ 1725606Snate@binkert.org assert(execContexts.size() == oldCPU->execContexts.size()); 1732SN/A 1749647Sdam.sunwoo@arm.com for (int i = 0; i < execContexts.size(); ++i) { 1759647Sdam.sunwoo@arm.com ExecContext *newXC = execContexts[i]; 1769647Sdam.sunwoo@arm.com ExecContext *oldXC = oldCPU->execContexts[i]; 1779647Sdam.sunwoo@arm.com 1789647Sdam.sunwoo@arm.com newXC->takeOverFrom(oldXC); 1799647Sdam.sunwoo@arm.com assert(newXC->cpu_id == oldXC->cpu_id); 1809749Sandreas@sandberg.pp.se#ifdef FULL_SYSTEM 1819749Sandreas@sandberg.pp.se system->replaceExecContext(newXC->cpu_id, newXC); 1829647Sdam.sunwoo@arm.com#else 1839647Sdam.sunwoo@arm.com assert(newXC->process == oldXC->process); 1841400SN/A newXC->process->replaceExecContext(newXC->cpu_id, newXC); 1855606Snate@binkert.org#endif 1865606Snate@binkert.org } 1872SN/A 1882SN/A for (int i = 0; i < NumInterruptLevels; ++i) 1892SN/A interrupts[i] = oldCPU->interrupts[i]; 1902SN/A intstatus = oldCPU->intstatus; 1916221Snate@binkert.org} 1926221Snate@binkert.org 1935606Snate@binkert.org 1946670Shsul@eecs.umich.edu#ifdef FULL_SYSTEM 1955606Snate@binkert.orgvoid 1962SN/ABaseCPU::post_interrupt(int int_num, int index) 1972SN/A{ 198124SN/A DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index); 1996221Snate@binkert.org 2006221Snate@binkert.org if (int_num < 0 || int_num >= NumInterruptLevels) 2016221Snate@binkert.org panic("int_num out of bounds\n"); 202124SN/A 203124SN/A if (index < 0 || index >= sizeof(uint8_t) * 8) 204124SN/A panic("int_num out of bounds\n"); 205124SN/A 2065606Snate@binkert.org AlphaISA::check_interrupts = 1; 2075606Snate@binkert.org interrupts[int_num] |= 1 << index; 2089749Sandreas@sandberg.pp.se intstatus |= (ULL(1) << int_num); 2099749Sandreas@sandberg.pp.se} 2105606Snate@binkert.org 211124SN/Avoid 2121400SN/ABaseCPU::clear_interrupt(int int_num, int index) 2135606Snate@binkert.org{ 214124SN/A DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index); 215124SN/A 216124SN/A if (int_num < 0 || int_num >= NumInterruptLevels) 217124SN/A panic("int_num out of bounds\n"); 2186221Snate@binkert.org 2196221Snate@binkert.org if (index < 0 || index >= sizeof(uint8_t) * 8) 2205606Snate@binkert.org panic("int_num out of bounds\n"); 2216221Snate@binkert.org 2225606Snate@binkert.org interrupts[int_num] &= ~(1 << index); 223124SN/A if (interrupts[int_num] == 0) 224124SN/A intstatus &= ~(ULL(1) << int_num); 2251191SN/A} 2265529Snate@binkert.org 2278634Schris.emmons@arm.comvoid 22811359Sandreas@sandberg.pp.seBaseCPU::clear_interrupts() 2298634Schris.emmons@arm.com{ 2301191SN/A DPRINTF(Interrupt, "Interrupts all cleared\n"); 2315529Snate@binkert.org 2321191SN/A memset(interrupts, 0, sizeof(interrupts)); 2335529Snate@binkert.org intstatus = 0; 2341191SN/A} 2351191SN/A 23612085Sspwilson2@wisc.edu#endif // FULL_SYSTEM 23712085Sspwilson2@wisc.edu 2385606Snate@binkert.org// 2391191SN/A// This declaration is not needed now that SamplingCPU provides a 2401191SN/A// BaseCPUBuilder object. 2418876Sandreas.hansson@arm.com// 2428876Sandreas.hansson@arm.com#if 0 2438876Sandreas.hansson@arm.comDEFINE_SIM_OBJECT_CLASS_NAME("BaseCPU", BaseCPU) 2449433SAndreas.Sandberg@ARM.com#endif 24511221Sandreas.sandberg@arm.com