base.cc revision 605
1/* 2 * Copyright (c) 2003 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#include <string> 30#include <sstream> 31#include <iostream> 32 33#include "cpu/base_cpu.hh" 34#include "base/cprintf.hh" 35#include "cpu/exec_context.hh" 36#include "base/misc.hh" 37#include "sim/param.hh" 38#include "sim/sim_events.hh" 39 40using namespace std; 41 42vector<BaseCPU *> BaseCPU::cpuList; 43 44// This variable reflects the max number of threads in any CPU. Be 45// careful to only use it once all the CPUs that you care about have 46// been initialized 47int maxThreadsPerCPU = 1; 48 49#ifdef FULL_SYSTEM 50BaseCPU::BaseCPU(const string &_name, int _number_of_threads, 51 Counter max_insts_any_thread, 52 Counter max_insts_all_threads, 53 Counter max_loads_any_thread, 54 Counter max_loads_all_threads, 55 System *_system, Tick freq) 56 : SimObject(_name), frequency(freq), 57 number_of_threads(_number_of_threads), system(_system) 58#else 59BaseCPU::BaseCPU(const string &_name, int _number_of_threads, 60 Counter max_insts_any_thread, 61 Counter max_insts_all_threads, 62 Counter max_loads_any_thread, 63 Counter max_loads_all_threads) 64 : SimObject(_name), number_of_threads(_number_of_threads) 65#endif 66{ 67 // add self to global list of CPUs 68 cpuList.push_back(this); 69 70 if (number_of_threads > maxThreadsPerCPU) 71 maxThreadsPerCPU = number_of_threads; 72 73 // allocate per-thread instruction-based event queues 74 comInstEventQueue = new (EventQueue *)[number_of_threads]; 75 for (int i = 0; i < number_of_threads; ++i) 76 comInstEventQueue[i] = new EventQueue("instruction-based event queue"); 77 78 // 79 // set up instruction-count-based termination events, if any 80 // 81 if (max_insts_any_thread != 0) 82 for (int i = 0; i < number_of_threads; ++i) 83 new SimExitEvent(comInstEventQueue[i], max_insts_any_thread, 84 "a thread reached the max instruction count"); 85 86 if (max_insts_all_threads != 0) { 87 // allocate & initialize shared downcounter: each event will 88 // decrement this when triggered; simulation will terminate 89 // when counter reaches 0 90 int *counter = new int; 91 *counter = number_of_threads; 92 for (int i = 0; i < number_of_threads; ++i) 93 new CountedExitEvent(comInstEventQueue[i], 94 "all threads reached the max instruction count", 95 max_insts_all_threads, *counter); 96 } 97 98 // allocate per-thread load-based event queues 99 comLoadEventQueue = new (EventQueue *)[number_of_threads]; 100 for (int i = 0; i < number_of_threads; ++i) 101 comLoadEventQueue[i] = new EventQueue("load-based event queue"); 102 103 // 104 // set up instruction-count-based termination events, if any 105 // 106 if (max_loads_any_thread != 0) 107 for (int i = 0; i < number_of_threads; ++i) 108 new SimExitEvent(comLoadEventQueue[i], max_loads_any_thread, 109 "a thread reached the max load count"); 110 111 if (max_loads_all_threads != 0) { 112 // allocate & initialize shared downcounter: each event will 113 // decrement this when triggered; simulation will terminate 114 // when counter reaches 0 115 int *counter = new int; 116 *counter = number_of_threads; 117 for (int i = 0; i < number_of_threads; ++i) 118 new CountedExitEvent(comLoadEventQueue[i], 119 "all threads reached the max load count", 120 max_loads_all_threads, *counter); 121 } 122 123#ifdef FULL_SYSTEM 124 memset(interrupts, 0, sizeof(interrupts)); 125 intstatus = 0; 126#endif 127} 128 129 130void 131BaseCPU::regStats() 132{ 133 int size = execContexts.size(); 134 if (size > 1) { 135 for (int i = 0; i < size; ++i) { 136 stringstream namestr; 137 ccprintf(namestr, "%s.ctx%d", name(), i); 138 execContexts[i]->regStats(namestr.str()); 139 } 140 } else if (size == 1) 141 execContexts[0]->regStats(name()); 142} 143 144 145void 146BaseCPU::registerExecContexts() 147{ 148 for (int i = 0; i < execContexts.size(); ++i) { 149 ExecContext *xc = execContexts[i]; 150 int cpu_id; 151 152#ifdef FULL_SYSTEM 153 cpu_id = system->registerExecContext(xc); 154#else 155 cpu_id = xc->process->registerExecContext(xc); 156#endif 157 158 xc->cpu_id = cpu_id; 159 } 160} 161 162 163void 164BaseCPU::switchOut() 165{ 166 // default: do nothing 167} 168 169void 170BaseCPU::takeOverFrom(BaseCPU *oldCPU) 171{ 172 assert(execContexts.size() == oldCPU->execContexts.size()); 173 174 for (int i = 0; i < execContexts.size(); ++i) { 175 ExecContext *newXC = execContexts[i]; 176 ExecContext *oldXC = oldCPU->execContexts[i]; 177 178 newXC->takeOverFrom(oldXC); 179 assert(newXC->cpu_id == oldXC->cpu_id); 180#ifdef FULL_SYSTEM 181 system->replaceExecContext(newXC->cpu_id, newXC); 182#else 183 assert(newXC->process == oldXC->process); 184 newXC->process->replaceExecContext(newXC->cpu_id, newXC); 185#endif 186 } 187 188 for (int i = 0; i < NumInterruptLevels; ++i) 189 interrupts[i] = oldCPU->interrupts[i]; 190 intstatus = oldCPU->intstatus; 191} 192 193 194#ifdef FULL_SYSTEM 195void 196BaseCPU::post_interrupt(int int_num, int index) 197{ 198 DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index); 199 200 if (int_num < 0 || int_num >= NumInterruptLevels) 201 panic("int_num out of bounds\n"); 202 203 if (index < 0 || index >= sizeof(uint8_t) * 8) 204 panic("int_num out of bounds\n"); 205 206 AlphaISA::check_interrupts = 1; 207 interrupts[int_num] |= 1 << index; 208 intstatus |= (ULL(1) << int_num); 209} 210 211void 212BaseCPU::clear_interrupt(int int_num, int index) 213{ 214 DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index); 215 216 if (int_num < 0 || int_num >= NumInterruptLevels) 217 panic("int_num out of bounds\n"); 218 219 if (index < 0 || index >= sizeof(uint8_t) * 8) 220 panic("int_num out of bounds\n"); 221 222 interrupts[int_num] &= ~(1 << index); 223 if (interrupts[int_num] == 0) 224 intstatus &= ~(ULL(1) << int_num); 225} 226 227void 228BaseCPU::clear_interrupts() 229{ 230 DPRINTF(Interrupt, "Interrupts all cleared\n"); 231 232 memset(interrupts, 0, sizeof(interrupts)); 233 intstatus = 0; 234} 235 236#endif // FULL_SYSTEM 237 238// 239// This declaration is not needed now that SamplingCPU provides a 240// BaseCPUBuilder object. 241// 242#if 0 243DEFINE_SIM_OBJECT_CLASS_NAME("BaseCPU", BaseCPU) 244#endif 245