SConscript revision 7087
12929Sktlim@umich.edu# -*- mode:python -*- 22929Sktlim@umich.edu 32932Sktlim@umich.edu# Copyright (c) 2006 The Regents of The University of Michigan 42929Sktlim@umich.edu# All rights reserved. 52929Sktlim@umich.edu# 62929Sktlim@umich.edu# Redistribution and use in source and binary forms, with or without 72929Sktlim@umich.edu# modification, are permitted provided that the following conditions are 82929Sktlim@umich.edu# met: redistributions of source code must retain the above copyright 92929Sktlim@umich.edu# notice, this list of conditions and the following disclaimer; 102929Sktlim@umich.edu# redistributions in binary form must reproduce the above copyright 112929Sktlim@umich.edu# notice, this list of conditions and the following disclaimer in the 122929Sktlim@umich.edu# documentation and/or other materials provided with the distribution; 132929Sktlim@umich.edu# neither the name of the copyright holders nor the names of its 142929Sktlim@umich.edu# contributors may be used to endorse or promote products derived from 152929Sktlim@umich.edu# this software without specific prior written permission. 162929Sktlim@umich.edu# 172929Sktlim@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 182929Sktlim@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 192929Sktlim@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 202929Sktlim@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 212929Sktlim@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 222929Sktlim@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 232929Sktlim@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 242929Sktlim@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 252929Sktlim@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 262929Sktlim@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 272929Sktlim@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282932Sktlim@umich.edu# 292932Sktlim@umich.edu# Authors: Steve Reinhardt 302932Sktlim@umich.edu 312929Sktlim@umich.eduImport('*') 326007Ssteve.reinhardt@amd.com 337735SAli.Saidi@ARM.com################################################################# 342929Sktlim@umich.edu# 352929Sktlim@umich.edu# Generate StaticInst execute() method signatures. 362929Sktlim@umich.edu# 372929Sktlim@umich.edu# There must be one signature for each CPU model compiled in. 382929Sktlim@umich.edu# Since the set of compiled-in models is flexible, we generate a 392929Sktlim@umich.edu# header containing the appropriate set of signatures on the fly. 402929Sktlim@umich.edu# 418947Sandreas.hansson@arm.com################################################################# 428947Sandreas.hansson@arm.com 438947Sandreas.hansson@arm.com# Template for execute() signature. 442929Sktlim@umich.eduexec_sig_template = ''' 452929Sktlim@umich.eduvirtual Fault execute(%(type)s *xc, Trace::InstRecord *traceData) const = 0; 462929Sktlim@umich.eduvirtual Fault eaComp(%(type)s *xc, Trace::InstRecord *traceData) const 472929Sktlim@umich.edu{ panic("eaComp not defined!"); M5_DUMMY_RETURN }; 482929Sktlim@umich.eduvirtual Fault initiateAcc(%(type)s *xc, Trace::InstRecord *traceData) const 492929Sktlim@umich.edu{ panic("initiateAcc not defined!"); M5_DUMMY_RETURN }; 506007Ssteve.reinhardt@amd.comvirtual Fault completeAcc(Packet *pkt, %(type)s *xc, 516007Ssteve.reinhardt@amd.com Trace::InstRecord *traceData) const 526007Ssteve.reinhardt@amd.com{ panic("completeAcc not defined!"); M5_DUMMY_RETURN }; 536007Ssteve.reinhardt@amd.com''' 546007Ssteve.reinhardt@amd.com 556007Ssteve.reinhardt@amd.commem_ini_sig_template = ''' 566007Ssteve.reinhardt@amd.comvirtual Fault eaComp(%(type)s *xc, Trace::InstRecord *traceData) const 576007Ssteve.reinhardt@amd.com{ panic("eaComp not defined!"); M5_DUMMY_RETURN }; 586007Ssteve.reinhardt@amd.comvirtual Fault initiateAcc(%s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); M5_DUMMY_RETURN }; 596007Ssteve.reinhardt@amd.com''' 606007Ssteve.reinhardt@amd.com 616007Ssteve.reinhardt@amd.commem_comp_sig_template = ''' 626007Ssteve.reinhardt@amd.comvirtual Fault completeAcc(uint8_t *data, %s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); return NoFault; M5_DUMMY_RETURN }; 636007Ssteve.reinhardt@amd.com''' 646007Ssteve.reinhardt@amd.com 656007Ssteve.reinhardt@amd.com# Generate a temporary CPU list, including the CheckerCPU if 669435SAndreas.Sandberg@ARM.com# it's enabled. This isn't used for anything else other than StaticInst 679435SAndreas.Sandberg@ARM.com# headers. 689435SAndreas.Sandberg@ARM.comtemp_cpu_list = env['CPU_MODELS'][:] 696007Ssteve.reinhardt@amd.com 706007Ssteve.reinhardt@amd.comif env['USE_CHECKER']: 716007Ssteve.reinhardt@amd.com temp_cpu_list.append('CheckerCPU') 726007Ssteve.reinhardt@amd.com SimObject('CheckerCPU.py') 736007Ssteve.reinhardt@amd.com 746007Ssteve.reinhardt@amd.com# Generate header. 756007Ssteve.reinhardt@amd.comdef gen_cpu_exec_signatures(target, source, env): 766007Ssteve.reinhardt@amd.com f = open(str(target[0]), 'w') 776007Ssteve.reinhardt@amd.com print >> f, ''' 786007Ssteve.reinhardt@amd.com#ifndef __CPU_STATIC_INST_EXEC_SIGS_HH__ 792929Sktlim@umich.edu#define __CPU_STATIC_INST_EXEC_SIGS_HH__ 802929Sktlim@umich.edu''' 812929Sktlim@umich.edu for cpu in temp_cpu_list: 826007Ssteve.reinhardt@amd.com xc_type = CpuModel.dict[cpu].strings['CPU_exec_context'] 836007Ssteve.reinhardt@amd.com print >> f, exec_sig_template % { 'type' : xc_type } 846007Ssteve.reinhardt@amd.com print >> f, ''' 859781Sandreas.hansson@arm.com#endif // __CPU_STATIC_INST_EXEC_SIGS_HH__ 866007Ssteve.reinhardt@amd.com''' 876007Ssteve.reinhardt@amd.com 882929Sktlim@umich.edu# Generate string that gets printed when header is rebuilt 892929Sktlim@umich.edudef gen_sigs_string(target, source, env): 902929Sktlim@umich.edu return "Generating static_inst_exec_sigs.hh: " \ 912929Sktlim@umich.edu + ', '.join(temp_cpu_list) 922929Sktlim@umich.edu 936011Ssteve.reinhardt@amd.com# Add command to generate header to environment. 946007Ssteve.reinhardt@amd.comenv.Command('static_inst_exec_sigs.hh', (), 956007Ssteve.reinhardt@amd.com Action(gen_cpu_exec_signatures, gen_sigs_string, 966007Ssteve.reinhardt@amd.com varlist = temp_cpu_list)) 976007Ssteve.reinhardt@amd.com 986007Ssteve.reinhardt@amd.comenv.Depends('static_inst_exec_sigs.hh', Value(env['USE_CHECKER'])) 996007Ssteve.reinhardt@amd.comenv.Depends('static_inst_exec_sigs.hh', Value(env['CPU_MODELS'])) 1006007Ssteve.reinhardt@amd.com 1016007Ssteve.reinhardt@amd.com# List of suppported CPUs by the Checker. Errors out if USE_CHECKER=True 1026007Ssteve.reinhardt@amd.com# and one of these are not being used. 1036007Ssteve.reinhardt@amd.comCheckerSupportedCPUList = ['O3CPU', 'OzoneCPU'] 1046007Ssteve.reinhardt@amd.com 1056007Ssteve.reinhardt@amd.comSimObject('BaseCPU.py') 1066007Ssteve.reinhardt@amd.comSimObject('FuncUnit.py') 10710742Sandreas.hansson@arm.comSimObject('ExeTracer.py') 10810742Sandreas.hansson@arm.comSimObject('IntelTrace.py') 10910384SCurtis.Dunham@arm.comSimObject('NativeTrace.py') 11010742Sandreas.hansson@arm.com 1116007Ssteve.reinhardt@amd.comSource('activity.cc') 1129781Sandreas.hansson@arm.comSource('base.cc') 1139781Sandreas.hansson@arm.comSource('cpuevent.cc') 1149781Sandreas.hansson@arm.comSource('exetrace.cc') 1159781Sandreas.hansson@arm.comSource('func_unit.cc') 1167735SAli.Saidi@ARM.comSource('inteltrace.cc') 1176011Ssteve.reinhardt@amd.comSource('nativetrace.cc') 1186007Ssteve.reinhardt@amd.comSource('pc_event.cc') 1199781Sandreas.hansson@arm.comSource('quiesce_event.cc') 1206007Ssteve.reinhardt@amd.comSource('static_inst.cc') 1216007Ssteve.reinhardt@amd.comSource('simple_thread.cc') 1227735SAli.Saidi@ARM.comSource('thread_context.cc') 1237735SAli.Saidi@ARM.comSource('thread_state.cc') 1247735SAli.Saidi@ARM.com 1257735SAli.Saidi@ARM.comif env['FULL_SYSTEM']: 1267735SAli.Saidi@ARM.com SimObject('IntrControl.py') 1277735SAli.Saidi@ARM.com 1287735SAli.Saidi@ARM.com Source('intr_control.cc') 1297735SAli.Saidi@ARM.com Source('profile.cc') 1307735SAli.Saidi@ARM.com 1317735SAli.Saidi@ARM.com if env['TARGET_ISA'] == 'sparc': 1327735SAli.Saidi@ARM.com SimObject('LegionTrace.py') 1337735SAli.Saidi@ARM.com Source('legiontrace.cc') 1347735SAli.Saidi@ARM.com 1357735SAli.Saidi@ARM.comif env['USE_CHECKER']: 1366007Ssteve.reinhardt@amd.com Source('checker/cpu.cc') 1378599Ssteve.reinhardt@amd.com TraceFlag('Checker') 1388599Ssteve.reinhardt@amd.com checker_supports = False 1398599Ssteve.reinhardt@amd.com for i in CheckerSupportedCPUList: 1406007Ssteve.reinhardt@amd.com if i in env['CPU_MODELS']: 1416011Ssteve.reinhardt@amd.com checker_supports = True 1426007Ssteve.reinhardt@amd.com if not checker_supports: 1436007Ssteve.reinhardt@amd.com print "Checker only supports CPU models", 1446007Ssteve.reinhardt@amd.com for i in CheckerSupportedCPUList: 1456007Ssteve.reinhardt@amd.com print i, 1466007Ssteve.reinhardt@amd.com print ", please set USE_CHECKER=False or use one of those CPU models" 1476007Ssteve.reinhardt@amd.com Exit(1) 1489781Sandreas.hansson@arm.com 1499781Sandreas.hansson@arm.comTraceFlag('Activity') 1509781Sandreas.hansson@arm.comTraceFlag('Commit') 1519781Sandreas.hansson@arm.comTraceFlag('Context') 1526007Ssteve.reinhardt@amd.comTraceFlag('Decode') 1536007Ssteve.reinhardt@amd.comTraceFlag('DynInst') 1546007Ssteve.reinhardt@amd.comTraceFlag('ExecEnable') 1559781Sandreas.hansson@arm.comTraceFlag('ExecCPSeq') 1569781Sandreas.hansson@arm.comTraceFlag('ExecEffAddr') 1579781Sandreas.hansson@arm.comTraceFlag('ExecFaulting', 'Trace faulting instructions') 1589781Sandreas.hansson@arm.comTraceFlag('ExecFetchSeq') 15910384SCurtis.Dunham@arm.comTraceFlag('ExecOpClass') 16010384SCurtis.Dunham@arm.comTraceFlag('ExecRegDelta') 16110384SCurtis.Dunham@arm.comTraceFlag('ExecResult') 1629781Sandreas.hansson@arm.comTraceFlag('ExecSpeculative') 1636008Ssteve.reinhardt@amd.comTraceFlag('ExecSymbol') 1646008Ssteve.reinhardt@amd.comTraceFlag('ExecThread') 1656008Ssteve.reinhardt@amd.comTraceFlag('ExecTicks') 1666008Ssteve.reinhardt@amd.comTraceFlag('ExecMicro') 1676008Ssteve.reinhardt@amd.comTraceFlag('ExecMacro') 1689401SAndreas.Sandberg@ARM.comTraceFlag('Fetch') 1699781Sandreas.hansson@arm.comTraceFlag('IntrControl') 1709781Sandreas.hansson@arm.comTraceFlag('PCEvent') 1716008Ssteve.reinhardt@amd.comTraceFlag('Quiesce') 1729781Sandreas.hansson@arm.com 1736007Ssteve.reinhardt@amd.comCompoundFlag('Exec', [ 'ExecEnable', 'ExecTicks', 'ExecOpClass', 'ExecThread', 1746007Ssteve.reinhardt@amd.com 'ExecEffAddr', 'ExecResult', 'ExecSymbol', 'ExecMicro', 'ExecFaulting' ]) 1756007Ssteve.reinhardt@amd.comCompoundFlag('ExecNoTicks', [ 'ExecEnable', 'ExecOpClass', 'ExecThread', 1766007Ssteve.reinhardt@amd.com 'ExecEffAddr', 'ExecResult', 'ExecMicro', 'ExecFaulting' ]) 1779781Sandreas.hansson@arm.com