SConscript revision 7087
12155SN/A# -*- mode:python -*-
22155SN/A
32155SN/A# Copyright (c) 2006 The Regents of The University of Michigan
42155SN/A# All rights reserved.
52155SN/A#
62155SN/A# Redistribution and use in source and binary forms, with or without
72155SN/A# modification, are permitted provided that the following conditions are
82155SN/A# met: redistributions of source code must retain the above copyright
92155SN/A# notice, this list of conditions and the following disclaimer;
102155SN/A# redistributions in binary form must reproduce the above copyright
112155SN/A# notice, this list of conditions and the following disclaimer in the
122155SN/A# documentation and/or other materials provided with the distribution;
132155SN/A# neither the name of the copyright holders nor the names of its
142155SN/A# contributors may be used to endorse or promote products derived from
152155SN/A# this software without specific prior written permission.
162155SN/A#
172155SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
182155SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
192155SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
202155SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
212155SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
222155SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
232155SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
242155SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
252155SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
262155SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
272155SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
282665Ssaidi@eecs.umich.edu#
292665Ssaidi@eecs.umich.edu# Authors: Steve Reinhardt
302155SN/A
314202Sbinkertn@umich.eduImport('*')
322155SN/A
332178SN/A#################################################################
342178SN/A#
352178SN/A# Generate StaticInst execute() method signatures.
362178SN/A#
372178SN/A# There must be one signature for each CPU model compiled in.
382178SN/A# Since the set of compiled-in models is flexible, we generate a
392178SN/A# header containing the appropriate set of signatures on the fly.
402178SN/A#
412178SN/A#################################################################
422178SN/A
432178SN/A# Template for execute() signature.
442178SN/Aexec_sig_template = '''
452155SN/Avirtual Fault execute(%(type)s *xc, Trace::InstRecord *traceData) const = 0;
462178SN/Avirtual Fault eaComp(%(type)s *xc, Trace::InstRecord *traceData) const
472155SN/A{ panic("eaComp not defined!"); M5_DUMMY_RETURN };
482155SN/Avirtual Fault initiateAcc(%(type)s *xc, Trace::InstRecord *traceData) const
492178SN/A{ panic("initiateAcc not defined!"); M5_DUMMY_RETURN };
502155SN/Avirtual Fault completeAcc(Packet *pkt, %(type)s *xc,
515865Sksewell@umich.edu                          Trace::InstRecord *traceData) const
525865Sksewell@umich.edu{ panic("completeAcc not defined!"); M5_DUMMY_RETURN };
533918Ssaidi@eecs.umich.edu'''
545865Sksewell@umich.edu
552623SN/Amem_ini_sig_template = '''
563918Ssaidi@eecs.umich.eduvirtual Fault eaComp(%(type)s *xc, Trace::InstRecord *traceData) const
575865Sksewell@umich.edu{ panic("eaComp not defined!"); M5_DUMMY_RETURN };
585865Sksewell@umich.eduvirtual Fault initiateAcc(%s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); M5_DUMMY_RETURN };
592155SN/A'''
602155SN/A
612292SN/Amem_comp_sig_template = '''
623918Ssaidi@eecs.umich.eduvirtual Fault completeAcc(uint8_t *data, %s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); return NoFault; M5_DUMMY_RETURN };
632292SN/A'''
642292SN/A
652292SN/A# Generate a temporary CPU list, including the CheckerCPU if
663918Ssaidi@eecs.umich.edu# it's enabled.  This isn't used for anything else other than StaticInst
672292SN/A# headers.
682292SN/Atemp_cpu_list = env['CPU_MODELS'][:]
692766Sktlim@umich.edu
702766Sktlim@umich.eduif env['USE_CHECKER']:
712766Sktlim@umich.edu    temp_cpu_list.append('CheckerCPU')
722921Sktlim@umich.edu    SimObject('CheckerCPU.py')
732921Sktlim@umich.edu
742766Sktlim@umich.edu# Generate header.
752766Sktlim@umich.edudef gen_cpu_exec_signatures(target, source, env):
765529Snate@binkert.org    f = open(str(target[0]), 'w')
772766Sktlim@umich.edu    print >> f, '''
784762Snate@binkert.org#ifndef __CPU_STATIC_INST_EXEC_SIGS_HH__
792155SN/A#define __CPU_STATIC_INST_EXEC_SIGS_HH__
802155SN/A'''
812155SN/A    for cpu in temp_cpu_list:
822155SN/A        xc_type = CpuModel.dict[cpu].strings['CPU_exec_context']
832155SN/A        print >> f, exec_sig_template % { 'type' : xc_type }
842155SN/A    print >> f, '''
852766Sktlim@umich.edu#endif  // __CPU_STATIC_INST_EXEC_SIGS_HH__
862155SN/A'''
875865Sksewell@umich.edu
882155SN/A# Generate string that gets printed when header is rebuilt
892155SN/Adef gen_sigs_string(target, source, env):
902155SN/A    return "Generating static_inst_exec_sigs.hh: " \
912155SN/A           + ', '.join(temp_cpu_list)
922178SN/A
932178SN/A# Add command to generate header to environment.
942178SN/Aenv.Command('static_inst_exec_sigs.hh', (),
952766Sktlim@umich.edu            Action(gen_cpu_exec_signatures, gen_sigs_string,
962178SN/A                   varlist = temp_cpu_list))
972178SN/A
982178SN/Aenv.Depends('static_inst_exec_sigs.hh', Value(env['USE_CHECKER']))
992178SN/Aenv.Depends('static_inst_exec_sigs.hh', Value(env['CPU_MODELS']))
1002766Sktlim@umich.edu
1012766Sktlim@umich.edu# List of suppported CPUs by the Checker.  Errors out if USE_CHECKER=True
1022766Sktlim@umich.edu# and one of these are not being used.
1032788Sktlim@umich.eduCheckerSupportedCPUList = ['O3CPU', 'OzoneCPU']
1042178SN/A
1052733Sktlim@umich.eduSimObject('BaseCPU.py')
1062733Sktlim@umich.eduSimObject('FuncUnit.py')
1072817Sksewell@umich.eduSimObject('ExeTracer.py')
1082733Sktlim@umich.eduSimObject('IntelTrace.py')
1094486Sbinkertn@umich.eduSimObject('NativeTrace.py')
1104486Sbinkertn@umich.edu
1114776Sgblack@eecs.umich.eduSource('activity.cc')
1124776Sgblack@eecs.umich.eduSource('base.cc')
1134486Sbinkertn@umich.eduSource('cpuevent.cc')
1144202Sbinkertn@umich.eduSource('exetrace.cc')
1154202Sbinkertn@umich.eduSource('func_unit.cc')
1164202Sbinkertn@umich.eduSource('inteltrace.cc')
1174202Sbinkertn@umich.eduSource('nativetrace.cc')
1184202Sbinkertn@umich.eduSource('pc_event.cc')
1194776Sgblack@eecs.umich.eduSource('quiesce_event.cc')
1204202Sbinkertn@umich.eduSource('static_inst.cc')
1214202Sbinkertn@umich.eduSource('simple_thread.cc')
1224202Sbinkertn@umich.eduSource('thread_context.cc')
1234202Sbinkertn@umich.eduSource('thread_state.cc')
1245217Ssaidi@eecs.umich.edu
1254202Sbinkertn@umich.eduif env['FULL_SYSTEM']:
1262155SN/A    SimObject('IntrControl.py')
1274202Sbinkertn@umich.edu
1284486Sbinkertn@umich.edu    Source('intr_control.cc')
1294486Sbinkertn@umich.edu    Source('profile.cc')
1304202Sbinkertn@umich.edu
1314202Sbinkertn@umich.edu    if env['TARGET_ISA'] == 'sparc':
1322821Sktlim@umich.edu        SimObject('LegionTrace.py')
1334776Sgblack@eecs.umich.edu        Source('legiontrace.cc')
1344776Sgblack@eecs.umich.edu
1354776Sgblack@eecs.umich.eduif env['USE_CHECKER']:
1364776Sgblack@eecs.umich.edu    Source('checker/cpu.cc')
1374776Sgblack@eecs.umich.edu    TraceFlag('Checker')
1384776Sgblack@eecs.umich.edu    checker_supports = False
1394776Sgblack@eecs.umich.edu    for i in CheckerSupportedCPUList:
1404776Sgblack@eecs.umich.edu        if i in env['CPU_MODELS']:
1412766Sktlim@umich.edu            checker_supports = True
1424202Sbinkertn@umich.edu    if not checker_supports:
1435192Ssaidi@eecs.umich.edu        print "Checker only supports CPU models",
1442733Sktlim@umich.edu        for i in CheckerSupportedCPUList:
1452733Sktlim@umich.edu            print i,
1462733Sktlim@umich.edu        print ", please set USE_CHECKER=False or use one of those CPU models"
1472733Sktlim@umich.edu        Exit(1)
1482733Sktlim@umich.edu
1492874Sktlim@umich.eduTraceFlag('Activity')
1502874Sktlim@umich.eduTraceFlag('Commit')
1512874Sktlim@umich.eduTraceFlag('Context')
1524202Sbinkertn@umich.eduTraceFlag('Decode')
1532733Sktlim@umich.eduTraceFlag('DynInst')
1545192Ssaidi@eecs.umich.eduTraceFlag('ExecEnable')
1555192Ssaidi@eecs.umich.eduTraceFlag('ExecCPSeq')
1565192Ssaidi@eecs.umich.eduTraceFlag('ExecEffAddr')
1575217Ssaidi@eecs.umich.eduTraceFlag('ExecFaulting', 'Trace faulting instructions')
1585192Ssaidi@eecs.umich.eduTraceFlag('ExecFetchSeq')
1595192Ssaidi@eecs.umich.eduTraceFlag('ExecOpClass')
1605192Ssaidi@eecs.umich.eduTraceFlag('ExecRegDelta')
1615192Ssaidi@eecs.umich.eduTraceFlag('ExecResult')
1625192Ssaidi@eecs.umich.eduTraceFlag('ExecSpeculative')
1635192Ssaidi@eecs.umich.eduTraceFlag('ExecSymbol')
1645192Ssaidi@eecs.umich.eduTraceFlag('ExecThread')
1655192Ssaidi@eecs.umich.eduTraceFlag('ExecTicks')
1665192Ssaidi@eecs.umich.eduTraceFlag('ExecMicro')
1675192Ssaidi@eecs.umich.eduTraceFlag('ExecMacro')
1685192Ssaidi@eecs.umich.eduTraceFlag('Fetch')
1695192Ssaidi@eecs.umich.eduTraceFlag('IntrControl')
1705192Ssaidi@eecs.umich.eduTraceFlag('PCEvent')
1715784Sgblack@eecs.umich.eduTraceFlag('Quiesce')
1725784Sgblack@eecs.umich.edu
1735192Ssaidi@eecs.umich.eduCompoundFlag('Exec', [ 'ExecEnable', 'ExecTicks', 'ExecOpClass', 'ExecThread',
1745192Ssaidi@eecs.umich.edu    'ExecEffAddr', 'ExecResult', 'ExecSymbol', 'ExecMicro', 'ExecFaulting' ])
1755192Ssaidi@eecs.umich.eduCompoundFlag('ExecNoTicks', [ 'ExecEnable', 'ExecOpClass', 'ExecThread',
1765192Ssaidi@eecs.umich.edu    'ExecEffAddr', 'ExecResult', 'ExecMicro', 'ExecFaulting' ])
1775192Ssaidi@eecs.umich.edu