SConscript revision 12653
14202Sbinkertn@umich.edu# -*- mode:python -*- 24202Sbinkertn@umich.edu 34202Sbinkertn@umich.edu# Copyright (c) 2006 The Regents of The University of Michigan 44202Sbinkertn@umich.edu# All rights reserved. 54202Sbinkertn@umich.edu# 64202Sbinkertn@umich.edu# Redistribution and use in source and binary forms, with or without 74202Sbinkertn@umich.edu# modification, are permitted provided that the following conditions are 84202Sbinkertn@umich.edu# met: redistributions of source code must retain the above copyright 94202Sbinkertn@umich.edu# notice, this list of conditions and the following disclaimer; 104202Sbinkertn@umich.edu# redistributions in binary form must reproduce the above copyright 114202Sbinkertn@umich.edu# notice, this list of conditions and the following disclaimer in the 124202Sbinkertn@umich.edu# documentation and/or other materials provided with the distribution; 134202Sbinkertn@umich.edu# neither the name of the copyright holders nor the names of its 144202Sbinkertn@umich.edu# contributors may be used to endorse or promote products derived from 154202Sbinkertn@umich.edu# this software without specific prior written permission. 164202Sbinkertn@umich.edu# 174202Sbinkertn@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 184202Sbinkertn@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 194202Sbinkertn@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 204202Sbinkertn@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 214202Sbinkertn@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 224202Sbinkertn@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 234202Sbinkertn@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 244202Sbinkertn@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 254202Sbinkertn@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 264202Sbinkertn@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 274202Sbinkertn@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 284202Sbinkertn@umich.edu# 294202Sbinkertn@umich.edu# Authors: Steve Reinhardt 304202Sbinkertn@umich.edu 314202Sbinkertn@umich.eduImport('*') 324202Sbinkertn@umich.edu 334295Sbinkertn@umich.eduif env['TARGET_ISA'] == 'null': 344295Sbinkertn@umich.edu SimObject('IntrControl.py') 354295Sbinkertn@umich.edu Source('intr_control_noisa.cc') 364295Sbinkertn@umich.edu Return() 374295Sbinkertn@umich.edu 384295Sbinkertn@umich.edu# Only build the protocol buffer instructions tracer if we have protobuf support 394295Sbinkertn@umich.eduif env['HAVE_PROTOBUF'] and env['TARGET_ISA'] != 'x86': 404295Sbinkertn@umich.edu SimObject('InstPBTrace.py') 414295Sbinkertn@umich.edu Source('inst_pb_trace.cc') 424295Sbinkertn@umich.edu 434295Sbinkertn@umich.eduSimObject('CheckerCPU.py') 444295Sbinkertn@umich.edu 454295Sbinkertn@umich.eduSimObject('BaseCPU.py') 464295Sbinkertn@umich.eduSimObject('CPUTracers.py') 474295Sbinkertn@umich.eduSimObject('FuncUnit.py') 484295Sbinkertn@umich.eduSimObject('IntrControl.py') 494295Sbinkertn@umich.eduSimObject('TimingExpr.py') 504295Sbinkertn@umich.edu 514295Sbinkertn@umich.eduSource('activity.cc') 524295Sbinkertn@umich.eduSource('base.cc') 534202Sbinkertn@umich.eduSource('cpuevent.cc') 544202Sbinkertn@umich.eduSource('exetrace.cc') 554202Sbinkertn@umich.eduSource('exec_context.cc') 564202Sbinkertn@umich.eduSource('func_unit.cc') 574202Sbinkertn@umich.eduSource('inteltrace.cc') 584202Sbinkertn@umich.eduSource('intr_control.cc') 594202Sbinkertn@umich.eduSource('nativetrace.cc') 604202Sbinkertn@umich.eduSource('pc_event.cc') 614202Sbinkertn@umich.eduSource('profile.cc') 624202Sbinkertn@umich.eduSource('quiesce_event.cc') 634202Sbinkertn@umich.eduSource('reg_class.cc') 644202Sbinkertn@umich.eduSource('static_inst.cc') 654202Sbinkertn@umich.eduSource('simple_thread.cc') 664202Sbinkertn@umich.eduSource('thread_context.cc') 674202Sbinkertn@umich.eduSource('thread_state.cc') 684202Sbinkertn@umich.eduSource('timing_expr.cc') 694202Sbinkertn@umich.edu 704202Sbinkertn@umich.eduSimObject('DummyChecker.py') 714202Sbinkertn@umich.eduSimObject('StaticInstFlags.py') 724202Sbinkertn@umich.eduSource('checker/cpu.cc') 734202Sbinkertn@umich.eduSource('dummy_checker.cc') 744202Sbinkertn@umich.eduDebugFlag('Checker') 754202Sbinkertn@umich.edu 764202Sbinkertn@umich.eduDebugFlag('Activity') 774202Sbinkertn@umich.eduDebugFlag('Commit') 784202Sbinkertn@umich.eduDebugFlag('Context') 794202Sbinkertn@umich.eduDebugFlag('Decode') 804202Sbinkertn@umich.eduDebugFlag('DynInst') 814202Sbinkertn@umich.eduDebugFlag('ExecEnable', 'Filter: Enable exec tracing (no tracing without this)') 824202Sbinkertn@umich.eduDebugFlag('ExecCPSeq', 'Format: Instruction sequence number') 834202Sbinkertn@umich.eduDebugFlag('ExecEffAddr', 'Format: Include effective address') 844202Sbinkertn@umich.eduDebugFlag('ExecFaulting', 'Trace faulting instructions') 854202Sbinkertn@umich.eduDebugFlag('ExecFetchSeq', 'Format: Fetch sequence number') 864202Sbinkertn@umich.eduDebugFlag('ExecOpClass', 'Format: Include operand class') 874202Sbinkertn@umich.eduDebugFlag('ExecRegDelta') 884202Sbinkertn@umich.eduDebugFlag('ExecResult', 'Format: Include results from execution') 894202Sbinkertn@umich.eduDebugFlag('ExecSymbol', 'Format: Try to include symbol names') 904202Sbinkertn@umich.eduDebugFlag('ExecThread', 'Format: Include thread ID in trace') 914202Sbinkertn@umich.eduDebugFlag('ExecTicks', 'Format: Include tick count') 924202Sbinkertn@umich.eduDebugFlag('ExecMicro', 'Filter: Include microops') 934202Sbinkertn@umich.eduDebugFlag('ExecMacro', 'Filter: Include macroops') 944202Sbinkertn@umich.eduDebugFlag('ExecUser', 'Filter: Trace user mode instructions') 954202Sbinkertn@umich.eduDebugFlag('ExecKernel', 'Filter: Trace kernel mode instructions') 964202Sbinkertn@umich.eduDebugFlag('ExecAsid', 'Format: Include ASID in trace') 974202Sbinkertn@umich.eduDebugFlag('ExecFlags', 'Format: Include instruction flags in trace') 984202Sbinkertn@umich.eduDebugFlag('Fetch') 994202Sbinkertn@umich.eduDebugFlag('IntrControl') 100DebugFlag('O3PipeView') 101DebugFlag('PCEvent') 102DebugFlag('Quiesce') 103DebugFlag('Mwait') 104 105CompoundFlag('ExecAll', [ 'ExecEnable', 'ExecCPSeq', 'ExecEffAddr', 106 'ExecFaulting', 'ExecFetchSeq', 'ExecOpClass', 'ExecRegDelta', 107 'ExecResult', 'ExecSymbol', 'ExecThread', 108 'ExecTicks', 'ExecMicro', 'ExecMacro', 'ExecUser', 'ExecKernel', 109 'ExecAsid', 'ExecFlags' ]) 110CompoundFlag('Exec', [ 'ExecEnable', 'ExecTicks', 'ExecOpClass', 'ExecThread', 111 'ExecEffAddr', 'ExecResult', 'ExecSymbol', 'ExecMicro', 'ExecMacro', 112 'ExecFaulting', 'ExecUser', 'ExecKernel' ]) 113CompoundFlag('ExecNoTicks', [ 'ExecEnable', 'ExecOpClass', 'ExecThread', 114 'ExecEffAddr', 'ExecResult', 'ExecMicro', 'ExecMacro', 'ExecFaulting', 115 'ExecUser', 'ExecKernel' ]) 116