SConscript revision 12653 
12632Sstever@eecs.umich.edu# -*- mode:python -*-
22632Sstever@eecs.umich.edu
32632Sstever@eecs.umich.edu# Copyright (c) 2006 The Regents of The University of Michigan
42632Sstever@eecs.umich.edu# All rights reserved.
52632Sstever@eecs.umich.edu#
62632Sstever@eecs.umich.edu# Redistribution and use in source and binary forms, with or without
72632Sstever@eecs.umich.edu# modification, are permitted provided that the following conditions are
82632Sstever@eecs.umich.edu# met: redistributions of source code must retain the above copyright
92632Sstever@eecs.umich.edu# notice, this list of conditions and the following disclaimer;
102632Sstever@eecs.umich.edu# redistributions in binary form must reproduce the above copyright
112632Sstever@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the
122632Sstever@eecs.umich.edu# documentation and/or other materials provided with the distribution;
132632Sstever@eecs.umich.edu# neither the name of the copyright holders nor the names of its
142632Sstever@eecs.umich.edu# contributors may be used to endorse or promote products derived from
152632Sstever@eecs.umich.edu# this software without specific prior written permission.
162632Sstever@eecs.umich.edu#
172632Sstever@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
182632Sstever@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
192632Sstever@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
202632Sstever@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
212632Sstever@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
222632Sstever@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
232632Sstever@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
242632Sstever@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
252632Sstever@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
262632Sstever@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
272632Sstever@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
282632Sstever@eecs.umich.edu#
292632Sstever@eecs.umich.edu# Authors: Steve Reinhardt
302632Sstever@eecs.umich.edu
312022SN/AImport('*')
322022SN/A
332022SN/Aif env['TARGET_ISA'] == 'null':
342022SN/A    SimObject('IntrControl.py')
352022SN/A    Source('intr_control_noisa.cc')
362022SN/A    Return()
372022SN/A
382022SN/A# Only build the protocol buffer instructions tracer if we have protobuf support
392022SN/Aif env['HAVE_PROTOBUF'] and env['TARGET_ISA'] != 'x86':
402022SN/A    SimObject('InstPBTrace.py')
412224SN/A    Source('inst_pb_trace.cc')
422458SN/A
433385Sgblack@eecs.umich.eduSimObject('CheckerCPU.py')
442224SN/A
452516SN/ASimObject('BaseCPU.py')
462022SN/ASimObject('CPUTracers.py')
472022SN/ASimObject('FuncUnit.py')
482022SN/ASimObject('IntrControl.py')
492022SN/ASimObject('TimingExpr.py')
502022SN/A
512713Ssaidi@eecs.umich.eduSource('activity.cc')
522022SN/ASource('base.cc')
532022SN/ASource('cpuevent.cc')
542022SN/ASource('exetrace.cc')
552022SN/ASource('exec_context.cc')
562224SN/ASource('func_unit.cc')
572224SN/ASource('inteltrace.cc')
582022SN/ASource('intr_control.cc')
592022SN/ASource('nativetrace.cc')
602022SN/ASource('pc_event.cc')
612022SN/ASource('profile.cc')
622022SN/ASource('quiesce_event.cc')
632022SN/ASource('reg_class.cc')
642022SN/ASource('static_inst.cc')
653069Sgblack@eecs.umich.eduSource('simple_thread.cc')
662022SN/ASource('thread_context.cc')
672022SN/ASource('thread_state.cc')
682022SN/ASource('timing_expr.cc')
692469SN/A
702469SN/ASimObject('DummyChecker.py')
712022SN/ASimObject('StaticInstFlags.py')
722022SN/ASource('checker/cpu.cc')
73Source('dummy_checker.cc')
74DebugFlag('Checker')
75
76DebugFlag('Activity')
77DebugFlag('Commit')
78DebugFlag('Context')
79DebugFlag('Decode')
80DebugFlag('DynInst')
81DebugFlag('ExecEnable', 'Filter: Enable exec tracing (no tracing without this)')
82DebugFlag('ExecCPSeq', 'Format: Instruction sequence number')
83DebugFlag('ExecEffAddr', 'Format: Include effective address')
84DebugFlag('ExecFaulting', 'Trace faulting instructions')
85DebugFlag('ExecFetchSeq', 'Format: Fetch sequence number')
86DebugFlag('ExecOpClass', 'Format: Include operand class')
87DebugFlag('ExecRegDelta')
88DebugFlag('ExecResult', 'Format: Include results from execution')
89DebugFlag('ExecSymbol', 'Format: Try to include symbol names')
90DebugFlag('ExecThread', 'Format: Include thread ID in trace')
91DebugFlag('ExecTicks', 'Format: Include tick count')
92DebugFlag('ExecMicro', 'Filter: Include microops')
93DebugFlag('ExecMacro', 'Filter: Include macroops')
94DebugFlag('ExecUser', 'Filter: Trace user mode instructions')
95DebugFlag('ExecKernel', 'Filter: Trace kernel mode instructions')
96DebugFlag('ExecAsid', 'Format: Include ASID in trace')
97DebugFlag('ExecFlags', 'Format: Include instruction flags in trace')
98DebugFlag('Fetch')
99DebugFlag('IntrControl')
100DebugFlag('O3PipeView')
101DebugFlag('PCEvent')
102DebugFlag('Quiesce')
103DebugFlag('Mwait')
104
105CompoundFlag('ExecAll', [ 'ExecEnable', 'ExecCPSeq', 'ExecEffAddr',
106    'ExecFaulting', 'ExecFetchSeq', 'ExecOpClass', 'ExecRegDelta',
107    'ExecResult', 'ExecSymbol', 'ExecThread',
108    'ExecTicks', 'ExecMicro', 'ExecMacro', 'ExecUser', 'ExecKernel',
109    'ExecAsid', 'ExecFlags' ])
110CompoundFlag('Exec', [ 'ExecEnable', 'ExecTicks', 'ExecOpClass', 'ExecThread',
111    'ExecEffAddr', 'ExecResult', 'ExecSymbol', 'ExecMicro', 'ExecMacro',
112    'ExecFaulting', 'ExecUser', 'ExecKernel' ])
113CompoundFlag('ExecNoTicks', [ 'ExecEnable', 'ExecOpClass', 'ExecThread',
114    'ExecEffAddr', 'ExecResult', 'ExecMicro', 'ExecMacro', 'ExecFaulting',
115    'ExecUser', 'ExecKernel' ])
116